Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
2+ years of hands-on RTL digital logic design experience using Verilog/System Verilog
Proficient in scripting languages (Python/Perl) for verification and automation
Experience in analyzing and optimizing PPA trade-offs in digital designs
Responsibilities
Design and implement sensor timing control logic for ISP integration
Participate in chip-level architecture definition and PPA trade-offs
Integrate and validate ISP data paths in accordance with design specs
Collaborate with project leads and engineers for system integration
Work with physical design teams on floor planning and timing closure
Perform full-chip integration and verification processes
Support chip bring-up, validation, and silicon debugging
Collaborate on image tuning and production readiness
Benefits
Opportunities for professional development and career advancement
Dynamic work environment with a focus on innovation
Collaborative culture with cross-disciplinary teamwork
Contributing to cutting-edge image sensor technology
Support for continuing education and skill enhancement
Full Job Description
Description
Key Responsibilities:
Design and implement sensor timing control logic and contribute to ISP system-level integration
Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs
Integrate and validate ISP data paths based on PRD, design specifications, and overall SoC architecture
Collaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validation
Work with physical design teams on floor planning, timing closure, and DFT implementation
Perform full-chip integration and verification
Support chip bring-up, validation, and silicon debugging
Collaborate with algorithm and application engineers on image tuning, optimization, and qualification
Support silicon validation, debugging, and image quality tuning through production readiness
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience
At least 2 years of hands-on experience designing RTL digital logic using Verilog/System Verilog, or equivalent industry experience
Proficiency with scripting languages such as Python or Perl to support design, verification, and automation workflows
Experience analyzing and optimizing area, power, and performance (PPA) trade-offs in digital designs
Preferred Qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related discipline
Strong background in image sensor and camera system design or integration
Practical experience with Image Signal Processing (ISP) architectures and pipelines
Annual base salary for this role in California, US is expected to be between $110,600 - $140,000. Actual pay will be determined on several factors such as relevant skills and experience, and the pay of employees in the similar role.
About OmniVision Technologies
OmniVision Technologies, Inc. is a leading developer of advanced digital imaging solutions. The company designs and manufactures image sensors and related technologies for a range of applications, including mobile devices, automotive, security, and medical imaging. OmniVision's products are used by leading manufacturers around the world, and the company is known for its innovation and expertise in the field of digital imaging. OmniVision was founded in 1995 and is headquartered in Santa Clara, California.
