Description
Overview :
Responsible for design, development, and refinement of Multi-Gbps PAM4 SerDes IP. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock designs is a significant plus.
Need to work closely with system and test engineers to develop high speed interface, package/board, and system clocks in image sensor and bridge chip products.
Responsibilities :
• Analog/Mixed-Signal design, simulation and verifications esp PAM4 receiver designs such as TI-SAR ADC, CTLE/DFE and other blocks in AFE.
• CDR design experience is significant plus.
• High speed test with scope and BERT.
• Layout design and support. Need to get involved into layout optimizations for high speed or high precision performance directly.
• Interface verifications between analog and digital.
• IP and design spec documentations.
Requirements :
• Familiar with Cadence analog design/layout flow and spice/spectreMDL simulations.
• Masters of Electrical Engineering or PhD with 3+ yrs of expertise.
Annual base salary for this role in California, US is expected to be between $150,000 - $250,000. Actual pay will be determined on a number of factors such as relevant skills, education, experience, and the pay of employees in the similar role.
