Job descriptionAs a Digital Design Engineer at Credo you are responsible for front-end ASIC design, including design and verification of complex logic blocks, and will collaborate with Physical Design and Integration teams to deliver successful tape-outs.
Base salary range is $80,000 - $133,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
QualificationsBasic Qualifications
- Bachelor's degree with two to seven years of experience, or Master's degree with up to five years of experience in Electrical/Electronic Engineering or Computer Engineering.
- Understanding of digital logic design and knowledge of handling complex synchronous and asynchronous interfaces.
- Knowledge of Verilog/SystemVerilog RTL design, through relevant experience or coursework projects.
- Knowledge of Verilog verification, through relevant experience or coursework projects.
- Knowledge of synthesis and static timing analysis, and of scripting languages such as Python, Tcl, Perl, and shell.
Preferred Qualifications
- Knowledge of UVM.
- Knowledge of the IEEE 802.3 Ethernet physical layer.
Job responsibilities- Write microarchitecture and/or design specifications, and architect, design, implement, and debug complex logic blocks.
- Understand and integrate complex IPs from internal and external IP vendors, and support front-end integration activities such as Lint, CDC, synthesis, and ECO.
- Develop functional tests and testbenches, and run functional RTL and gate-level verification and simulations.
- Work with ASIC design and verification, DFT, and physical design engineers to achieve a successful tape-out.
- Collaborate with Software, Firmware, Applications, and Systems teams to ensure a high-quality product, and bring up, validate, and debug functional features in the chip.
