GlobalFoundries

DFT Engineer

GlobalFoundries$106K — $184K *
Technical Services
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • 4+ years of hands-on DFT experience on SoCs, including ATPG, MBIST, LBIST, and scan-based testing
  • Proficiency with EDA tools like Synopsys TestMAX, Cadence Modus, or Mentor Tessent
  • Experience with scripting languages (Python, Perl, TCL) for automation and data analysis
  • Familiarity with optimizing test time, fault coverage, and ATPG patterns
  • Strong analytical skills with attention to detail for debugging
  • Effective communication skills for cross-team collaboration

Responsibilities

  • Implement DFT architectures including ATPG, MBIST, LBIST, and analog test features
  • Execute test pattern generation and optimization to minimize test time and maximize yield
  • Apply standardized DFT methodologies for efficient, repeatable results
  • Integrate DFT requirements into RTL and physical design stages with design and verification teams
  • Develop automation scripts for test pattern creation and analysis
  • Analyze test data to identify improvements and support debugging
  • Document DFT implementations and share knowledge within the team

Benefits

  • Support for Environmental, Health, Safety & Security programs
  • Opportunities for professional development and skill enhancement
  • Collaborative team environment for cross-functional projects
Full Job Description
The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG, MBIST, LBIST, and analog test solutions-while implementing optimized methodologies for rapid test pattern generation and efficient project delivery.

Your Job

  • Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features under manager guidance.


  • Execute test pattern generation and optimization to minimize test time while maximizing coverage and manufacturing yield.


  • Apply standardized DFT methodologies and flows to deliver efficient, repeatable results across multiple projects.


  • Integrate DFT requirements into RTL and physical design stages through collaboration with design, verification, and backend teams.


  • Develop automation scripts (TCL, Python, Perl) for test pattern creation, validation, and analysis.


  • Analyze test data from silicon bring-up and production to identify improvements and support root-cause debugging.


  • Document DFT implementations, test results, and reuse IP for team knowledge sharing.


Other Responsibilities

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.


Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.


  • 4+ years of hands-on DFT experience on SoCs, including ATPG, MBIST, LBIST, and scan-based testing.


  • Proficiency with EDA tools such as Synopsys TestMAX, Cadence Modus, or Mentor Tessent for DFT insertion and pattern generation.


  • Experience with scripting languages (Python, Perl, TCL) for flow automation and data analysis.


  • Familiarity with optimizing test time, fault coverage, and ATPG patterns.


  • Strong analytical skills and attention to detail for debugging complex test failures.


  • Effective communication skills for cross-functional collaboration.


Preferred Qualifications

  • Experience with automotive ASIL flows or high-volume manufacturing test challenges.


  • Proactive contributor to process improvements and tool evaluations.


Expected Salary Range
$106,000.00 - $184,000.00

The exact Salary will be determined based on qualifications, experience and location.

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