Cadence Design Systems

Design Architect Analog IC Designer

Cadence Design Systems$125K — $150K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Minimum 10 years of experience designing CMOS SerDes or high-speed I/O ICs.
  • Thorough understanding of jitter and signal equalization techniques.
  • Proficient in designing a range of SerDes circuits like drivers, receivers, and PLLs.
  • Excellent problem-solving abilities and strong communication skills.
  • Familiarity with common SerDes standards and their electrical requirements is a plus.
  • Proficient in circuit simulation and post-layout verification CAD tools; layout proficiency is a plus.
  • Experience with Cadence tools and testing at 64Gbps in 16nm technologies.
  • Master's or PhD in Electrical Engineering.

Responsibilities

  • Design and develop analog/mixed-signal IC circuit blocks from concept to final verification.
  • Contribute to the design of long-reach SerDes.
  • Ensure compliance with customer specifications through thorough verification.
  • Collaborate effectively within a team to solve design challenges.
  • Utilize CAD tools for circuit simulation and perform post-layout verifications.
  • Conduct lab tests to confirm design functionality and performance.
  • Stay updated on SerDes technologies and incorporate relevant standards in designs.

Benefits

  • Comprehensive health insurance coverage.
  • 401(k) retirement plan with company match.
  • Flexible work hours and remote work options.
  • Professional development and training opportunities.
  • Collaborative and innovative work environment.
Full Job Description
This role is for an existing vacancy.

Job Description

The Design Architect Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. The Design Architect Analog IC Designer contributes to the design of long-reach SerDes.
  • Candidate's background should include a minimum of 10 years of experience in the development of CMOS SerDes or high-speed I/O IC
  • Must have a thorough understanding of jitter and signal equalization techniques
  • Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
  • Excellent problem-solving skills, good communication skills, and ability to work cooperatively in a team environment
  • Working knowledge of a set of common SerDes standards and their electrical requirements is a plus
  • Position requires proficiency in using CAD tools for circuit simulation, and post-layout verification. Proficiency with layout entry a plus
  • Cadence tool experience, lab test experience, and design experience at 64Gbps and in 16nm technologies
  • MS or PhD in EE


Description de L'Emploi
L'Architecte en Conception de Circuits IntE9grE9s Analogiques est responsable de la conception et du dE9veloppement de circuits analogiques/mixtes, de l'architecture et de la spE9cification initiale jusqu'E0 la vE9rification finale de la conformitE9 aux spE9cifications du client. L'Architecte en Conception contribue E0 la conception de SerDes (Serialiseur/Deserialiseur) de longue portE9e.
  • Le candidat doit avoir au minimum 10 ans d'expE9rience dans le dE9veloppement de circuits intE9grE9s CMOS SerDes.
  • Doit avoir une comprE9hension approfondie du jitter et des techniques d'E9galisation du signal.
  • ExpE9rience dans la conception de la plupart des blocs de circuits SerDes : TX, RX, sE9rialiseur, dE9sE9rialiseur, interpolateur de phase, PLL, distribution d'horloge E0 haute vitesse, ADC et DAC, circuits de polarisation et de rE9fE9rence de tension (Bandgap), et rE9gulateurs de tension.
  • Excellentes compE9tences en rE9solution de problE8mes, bonnes capacitE9s de communication et aptitude E0 travailler en E9quipe.
  • Une connaissance pratique d'un ensemble de normes SerDes courantes et de leurs exigences E9lectriques est un atout.
  • Le poste nE9cessite la maEEtrise des outils CAD pour la simulation de circuits et la vE9rification post-layout. La maEEtrise de layout est un plus.
  • Une expE9rience avec les outils Cadence, les tests en laboratoire, ainsi que la conception E0 des vitesses 216 Gbps et dans des technologies 16 nm.
  • DiplF4me de M.Sc ou Ph.D. en gE9nie E9lectrique.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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