Job Area:Engineering Group, Engineering Group > Systems Engineering
General Summary:The Clocking Systems Staff Engineer is responsible for developing industry-leading DSP and mixed-signal SerDes architectures and solutions, with a focus on clock generation, clock recovery, timing synchronization. The engineer works closely with analog, digital, firmware, and validation teams to model, analyze, validate, and optimize clocking systems used in advanced high-speed communication products.
This role involves developing behavioral models, analyzing system performance and architectural tradeoffs, driving model-to-silicon correlation, and improving simulation and verification efficiency through automation and regression frameworks. The engineer contributes to the development of robust, high-performance clocking solutions across multiple product generations.
What You'll Do- Develop industry-leading DSP and mixed-signal SerDes architectures and solutions, with specialization in clock generation, clock recovery, and timing synchronization.
- Develop and maintain behavioral and system-level models for PLLs, CDRs, Retimers, clock distribution networks, and related timing circuits.
- Analyze system performance and architectural tradeoffs, identify design margins, and develop regression test frameworks to validate performance across multiple projects.
- Support silicon bring-up and model-to-silicon correlation, including investigation of clocking-related performance issues.
- Improve simulation efficiency and engineering productivity through model optimization, code enhancements, and automation of verification and regression workflows.
- Collaborate with analog, digital, firmware, and validation teams to ensure successful implementation and integration of clocking solutions.
- Document technical analyses, architecture decisions, and validation results.
What You'll Need:- 4+ years of relevant industry experience, or equivalent advanced academic experience, in clocking systems, mixed-signal design, SerDes, or related areas.
- Strong understanding of:
- Digital / mixed signal PLLs and clocking architectures
- Clock and Data Recovery (CDR) Architectures
- Jitter and phase noise analysis
- Clocking related adaptations and calibrations
- Experience developing behavioral or system-level models using MATLAB, Python, and SystemVerilog.
- Excellent communication and collaboration skills.
Preferred Qualifications- Master's or Ph.D. in Electrical Engineering or related field.
- Experience with DSP-based 112G, 224G, or higher-speed SerDes architectures.
- Knowledge of analog and mixed-signal PLL building blocks, including phase detectors, phase interpolators, and digitally controlled oscillators (DCOs).
- Experience with digital design and RTL development, including bit-accurate modeling and efficient hardware implementation techniques.
- Experience with silicon validation and model-to-silicon correlation.
Pay range and Other Compensation & Benefits:$110,500.00 - $160,500.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.
