Cadence Design Systems

ATE Test Engineering Architect

Cadence Design Systems$178K — $331K *
Information Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • BS with 12+ years, MS with 10+ years, or PhD with 8+ years of experience
  • Hands-on experience in CP/FT test program development
  • Experience with Advantest 93K ATE platform
  • Solid understanding of DFT and silicon debug
  • Proven experience in production support and coordination with offshore test partners
  • Strong problem-solving and cross-functional communication skills

Responsibilities

  • Lead ATE test development for wafer sort (CP) and final test (FT)
  • Drive first-silicon bring-up, debug, and characterization
  • Define test coverage, binning, guard-banding, and production release criteria
  • Analyze yield and failure data to implement quality improvements
  • Partner with DFT, design, OSATs, and test houses for manufacturable solutions
  • Support qualification, production ramp, and sustained manufacturing
  • Mentor engineers and act as a technical test leader across product teams

Benefits

  • Paid vacation and paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Variety of medical, dental, and vision plan options
  • Incentive compensation: bonuses and equity options
Full Job Description

We are seeking a ATE Test Engineering Architect to lead development and deployment of production test solutions for our large complex SoCs deployed in our Emulation Products. This role owns ATE test strategy and execution from first silicon bring‑up through qualification and high‑volume manufacturing, working closely with design, DFT, and global manufacturing partners.

This is a hands‑on technical leadership role for engineers passionate about silicon quality, yield, and scalable test solutions.

Job Responsibilities:

  • Lead ATE test development for wafer sort (CP) and final test (FT)
  • Drive first‑silicon bring‑up, debug, and characterization
  • Define test coverage, binning, guard‑banding, and production release criteria
  • Analyze yield and failure data; drive test‑related yield and quality improvements
  • Partner with DFT, design, OSATs, and test houses to ensure manufacturable solutions
  • Support qualification, production ramp, and sustained manufacturing
  • Mentor engineers and act as a technical test leader across product teams

Job Qualifications:

  • BS with a minimum of 12 years of experience OR MS with a minimum of 10 years of experience OR PhD with a minimum of 8 years of experience
  • Strong hands‑on experience with CP/FT test program development
  • Experience with Advantest 93K ATE platform
  • Solid understanding of DFT and silicon debug
  • Proven experience supporting production and working with offshore test partners
  • Strong problem‑solving and cross‑functional communication skills

The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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