15+ years of experience in IC design implementation and signoff, managing large-scale technical programs.
BS/MS in Electrical Engineering, Computer Engineering, or related field.
Deep expertise in digital design fundamentals and advanced node STA & ECOs (3nm and below).
Core timing signoff expertise and constraints debugging for hierarchical & 3DIC design.
Proven track record of leading technical teams and driving customer success at executive levels.
Strong proficiency in scripting (Tcl, Python, Perl) for design closure.
Excellent communication and leadership skills to influence stakeholders.
Responsibilities
Lead technical engagements with customers to drive adoption of Cadence's signoff portfolio.
Collaborate with R&D and Product Engineering to enhance tools based on customer needs.
Drive benchmarks and flow optimizations for timing signoff and closure methodologies.
Represent Cadence at industry forums and author technical papers to establish thought leadership.
Deliver keynote presentations to position Cadence as a market leader.
Benefits
Paid vacation and holidays.
401(k) plan with employer match.
Employee stock purchase plan.
Variety of medical, dental, and vision plan options.
Full Job Description
Key Responsibilities
Technical Expertise: Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio. Work closely with design teams to meet customer success metrics, guide adoption of Cadence's timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure.
Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.
Qualifications
15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
BS/MS in Electrical Engineering, Computer Engineering, or related field.
Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
Proven track record of leading technical teams and driving customer success at executive levels.
Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.
The annual salary range for Washington is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
About Cadence Design Systems
Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
