10+ years in semiconductor development, including 3+ years as a TPM or program lead on complex ASIC or SoC architectures.
Excellent communication and stakeholder management skills; ability to influence without authority.
Experience in companies with complex software/hardware integration.
Proven track record managing internationally distributed engineering teams.
Proficiency with program management tools such as Jira, Asana or Linear.
Experience with every element of the silicon life-cycle from architecture to post-silicon validation.
Ability to think out-of-the-box to find solutions.
Responsibilities
Break down company objectives into actionable milestones across the engineering org.
Own the schedule across the silicon development cycle, including architecture, verification, and post-silicon validation.
Coordinate efforts across teams in multiple international locations.
Define metrics and create dashboards to track progress and surface information.
Identify and mitigate risks to delivery schedules and quality.
Synthesize complex technical status and trade-offs into clear updates for executive leadership.
Benefits
Collaborative work environment with international teams.
Opportunity to influence high-level engineering decisions.
Access to cutting-edge technology and methodologies in semiconductor development.
Professional growth opportunities in a dynamic field.
Potential for involvement in innovative projects related to AI and advanced packaging.
Full Job Description
The Role
In partnership with our engineering leads, you will break down company objectives into actionable milestones across the engineering org. You will own the schedule across the entire silicon development lifecycle. You will surface information in a digestible format so that engineering executives are acutely aware of the current state of the project. You will also help to resolve issues across teams. Your work will ensure we ship on time. What You Will Own
Break down company objectives into actionable milestones across the engineering org.
Own the schedule across the silicon development cycle: architecture, micro-architecture, RTL generation, verification, logic synthesis, design for test, physical design, physical verification, tapeout, packaging, post-silicon testing, bring-up and post-silicon validation.
Coordinate these efforts across our teams in Mountain View, New York, London, Zurich and Copenhagen.
Define metrics, create dashboards and other mechanisms to surface information and track progress.
Identify and mitigate risks to delivery schedules and quality.
Synthesize complex technical status, trade-offs, and risks into clear updates for executive leadership.
What Makes You a Great Fit
10+ years in semiconductor development, including 3+ years as a TPM or program lead on complex ASIC or SoC architectures.
Excellent communication and stakeholder management skills; ability to influence without authority.
Experience in companies with complex software/hardware integration.
Proven track record managing internationally distributed engineering teams.
Proficiency with program management tools such as Jira, Asana or Linear.
Experience with every element of the silicon life-cycle from architecture and RTL generation to verification, tapeout, bring-up and post-silicon validation.
Ability to think out-of-the-box to find solutions.
Bonus Points
Ph.D. in an electrical engineering discipline.
Familiarity with chiplets and 3D packaging.
Expert at using Linear for program management tracking.
Familiarity with heterogeneous systems used for AI inference.
Experience working with external silicon foundries, Tier II vendors and OSAT vendors.
