Job Description:The Mixed-Signal and Linear Division (MSLD) is seeking a highly experienced
Technical Staff Validation Engineer specializing in Delta-Sigma ADCs and precision mixed-signal products. This role requires deep hands-on expertise in analog and mixed-signal hardware, precision measurement techniques, and system-level validation.
The ideal candidate will have extensive experience developing validation strategies and hardware test solutions for high-resolution ADCs, with strong knowledge of
Delta-Sigma architectures, signal integrity, low-noise measurement techniques, clocking, reference design, and dynamic/static ADC performance characterization.
As a senior technical contributor, this engineer will lead complex validation activities from first silicon through product release, partner closely with Design and Applications teams to resolve silicon and system-level issues and develop scalable hardware and automation solutions that improve validation capability and efficiency.
Key Responsibilities- Lead the development and execution of comprehensive silicon validation and characterization strategies for Delta-Sigma ADCs and precision mixed-signal products.
- Define validation requirements and methodologies for key ADC performance parameters, including SNR, SINAD, THD, THD+N, SFDR, ENOB, INL, DNL, offset, gain error, noise, linearity, input bandwidth, and reference performance.
- Design and develop precision bench-level hardware, evaluation boards, test fixtures, signal-conditioning circuitry, and automated measurement platforms for high-resolution ADC characterization.
- Develop measurement methodologies that properly address clock integrity, jitter, grounding, shielding, power-supply noise, reference noise, signal integrity, coherent sampling, FFT analysis, and measurement-system noise floors.
- Perform detailed characterization across voltage, temperature, frequency, sampling rate, gain, operating mode, and other applicable operating conditions.
- Work closely with Design Engineering to understand Delta-Sigma ADC architectures, analog front ends, references, clocking, digital filters, decimation, and device operating modes, translating architectural requirements into measurable silicon performance.
- Lead first-silicon bring-up and complex hardware and silicon debug, isolating issues between the DUT, test hardware, instrumentation, firmware/software, and silicon design.
- Analyze bench data to identify performance limitations, anomalies, and root causes, and collaborate with Design Engineering on corrective actions and design improvements.
- Develop automated characterization environments using NI PXI/PXIe instrumentation, LabVIEW, Python, MATLAB, or equivalent platforms to improve measurement repeatability, throughput, and data analysis.
- Correlate bench measurements with design expectations, simulation results, datasheet specifications, and other available validation or production data.
- Provide technically rigorous characterization data and analysis to support datasheets, application documentation, product qualification, and release decisions.
- Participate in architecture, design, and validation reviews, providing senior-level input on testability, measurement methodology, hardware architecture, validation coverage, and product risk.
- Provide technical leadership and mentorship to validation engineers in precision measurement, ADC characterization, test hardware development, debugging, and automation best practices.
- Drive improvements in validation hardware, methodologies, instrumentation, automation, and reusable test platforms across multiple product developments.
Requirements/Qualifications:Requirements / Qualifications- Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related discipline; Master's degree preferred.
- 12+ years of hands-on experience in semiconductor validation, characterization, mixed-signal test, or a closely related engineering discipline.
- Deep understanding of Delta-Sigma ADCs, including oversampling, quantization noise, noise shaping, decimation filters, digital filtering, sampling theory, aliasing, and ADC noise mechanisms.
- Strong understanding of ADC performance characterization, including: SNR / SINAD, THD / THD+N, SFDR, ENOB, FFT-based dynamic analysis, INL / DNL, Offset and gain error, Noise and noise spectral density, and Reference and power-supply sensitivity
- Strong hands-on analog hardware skills, including schematic interpretation, PCB bring-up, signal integrity, grounding, shielding, power integrity, low-noise design, clock distribution, reference circuits, and precision signal conditioning.
- Extensive experience using laboratory instrumentation such as precision signal generators, Audio Precision analyzers, oscilloscopes, spectrum analyzers, digital multimeters, power supplies, and NI PXI/PXIe instrumentation.
- Strong understanding of measurement-system limitations, including instrument noise floor, harmonic distortion, clock jitter, impedance/loading, cabling, grounding, fixture parasitics, and source/DUT interactions.
- Experience developing automated validation systems using LabVIEW, Python, MATLAB, or similar environments.
- Experience with common digital interfaces such as SPI, I²C, and other device-control interfaces used for silicon configuration and test
- Strong debugging and root-cause analysis skills with the ability to differentiate silicon behavior from test-system, hardware, instrumentation, or software limitations.
- Ability to independently solve complex mixed-signal measurement problems while collaborating effectively with Design, Applications, Product, Test, and Validation Engineering teams.
- Strong written and verbal communication skills with the ability to communicate complex technical findings to both engineering teams and technical leadership.
- Demonstrated ability to provide technical direction, mentorship, and leadership across validation activities and multiple product developments.
Travel Time:0% - 25%
Physical Attributes:Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:80% Sitting, 10% walking, 10% Standing
