Role Summary:The Fellow and Technical Lead, NPU serves as CARIAD's senior technical authority for automotive neural processing unit (NPU) architecture, microarchitecture and integration into the system-on-chip (SoC). The role provides advanced architectural leadership, influences critical technical decisions across the NPU and broader SoC development environment, and translates AI workloads and product requirements into NPU designs. The Fellow is responsible for leading technical execution through validation and production readiness, applying deep SoC architecture experience to ensure the NPU operates effectively within the complete SoC. As technical team lead, the Fellow provides architectural direction and technical leadership across the NPU engineering disciplines, including architecture, machine learning, compiler and toolchain, hardware design, RTL, design verification, FPGA, embedded software and technical program coordination. The role is accountable for delivering an NPU product that meets agreed functionality, performance, power, quality and schedule targets, including successful SoC integration. The Fellow exercises significant technical influence across participating engineering teams and development partners while operating within established product, program, and organizational decision-making structures.
Role Responsibilities:Technical Lead Responsibilities - Serve as the senior technical authority for NPU design, architecture, interfaces, and key implementation decisions; evaluate and challenge architectural assumptions, recommend changes to the broader SoC architecture where warranted, and align significant cross-domain decisions with appropriate SoC and engineering leadership.
- Align NPU solutions with product, platform and vehicle requirements, including applicable safety, security and quality constraints.
- Translate AI workload and product requirements into NPU designs and SoC integration plan
- Lead NPU architecture, design and code reviews; approve technical proposals and changes within the role's defined authority; and provide expert recommendations on major architectural changes requiring broader engineering alignment or approval.
- Identify, communicate and mitigate NPU performance, implementation and integration risks; escalate cross-domain dependencies.
- Act as the NPU technical interface to SoC engineering, technical program management, software, safety, security, quality and development partners.
- Set technical standards for modeling, design, verification, software quality and documentation across the NPU team.
- Direct and coordinate the NPU team's technical work, resolve cross-functional issues and ensure that team deliverables meet product requirements.
- Provide independent technical assessments and recommendations to senior engineering leadership on critical NPU architecture decisions, significant design tradeoffs, and technical risks with implications for SoC performance, integration, or product delivery.
NPU Architechture and SoC Integration Execution- Define and lead the NPU architecture and technical roadmap for automotive AI workloads, exercising independent architectural judgment and influencing the overall SoC strategy through recommendations on performance, scalability, integration, and technology tradeoffs.
- Own NPU product delivery from architecture through RTL, verification, SoC integration and post-silicon validation; align milestones and dependencies with technical program management.
- Define NPU and supporting IP requirements and technical criteria for supplier evaluation and selection.
- Own NPU architecture and behavior specifications, including compute, memory, dataflow, interfaces and integration requirements.
- Define supported AI use cases, numerical precision, performance targets and acceptance criteria with product and software teams.
- Provide technical leadership across SoC, RTL, physical design and software disciplines to evaluate and resolve complex architecture and implementation tradeoffs, challenge technical assumptions, and influence cross-domain decisions affecting NPU and SoC performance.
- Lead technical evaluation of NPU-related IP, technology alternatives, and engineering partners; provide authoritative technical recommendations influencing architecture selection, supplier decisions, and technical scope, while supporting Procurement on licensing and commercial considerations.
- Define NPU integration requirements for NoC, memory, clocks, resets, power management, interrupts, safety and security.
- Model NPU and full-SoC performance, bandwidth, power and area; validate assumptions using representative workloads and prototypes.
- Guide compiler, runtime and embedded software development alongside NPU microarchitecture and RTL design.
- Incorporate automotive functional safety, security and diagnostic requirements into the NPU design and its SoC integration.
- Lead NPU verification and validation planning at block, subsystem and SoC levels, including FPGA or emulation-based evaluation.
- Lead NPU bring-up, performance and power characterization, issue resolution and production-readiness reviews against agreed product acceptance criteria.
- Evaluate architectural alternatives and emerging NPU technologies to identify opportunities for improved technical performance, product capability, and development efficiency, incorporating recommendations into the NPU roadmap and relevant SoC architecture discussions.
Technical Team Leadership and Product Delivery- Lead technical reviews of semiconductor and engineering partners and assess their ability to deliver NPU requirements.
- Define the technical capabilities needed to deliver the NPU product and support technical hiring assessments and capability development.
- Develop NPU engineering methods, design standards and shared technical knowledge across the team and relevant SoC interfaces
- Ensure NPU technical decisions follow applicable engineering, product compliance and safety processes; escalate exceptions to the responsible owners.
- Coach engineers, review technical deliverables and provide feedback that strengthens engineering quality and team capability.
- Resolve technical risks and supplier dependencies; align mitigation actions and resource priorities with the NPU delivery plan.
- Serve as a senior technical advisor to engineering leadership and cross-functional technical teams, providing expert guidance on complex design challenges, architectural tradeoffs, and technical decisions beyond the immediate responsibilities of individual NPU engineering disciplines.
- Strengthen technical capability across the NPU development organization through mentorship, knowledge sharing, architectural guidance, and the promotion of engineering standards and practices that support consistent technical quality and effective collaboration.
General Skills:- Strong organizational and delegation skills, ensuring effective project execution and accountability.
- Actively listens with openness and empathy to uncover underlying intentions and motivations, facilitating constructive dialogue and conflict resolution.
- Excellent communication skills-verbal, written, and presentation-to effectively collaborate with technical and non-technical stakeholders.
- Fosters alignment among people, processes, and systems to sustain momentum and achieve shared goals, while anticipating and resolving
- Strong collaboration and influencing skills to drive cross-functional alignment on resource allocation, project planning, and strategy.
Required Specialized Skills:- Proven technical leadership in NPU or AI accelerator architecture and end-to-end SoC development.
- Track record as lead architect for production SoC tape-outs, including integration of complex compute or accelerator subsystems.
- SoC architecture and integration experience is required: this role develops the NPU as a subsystem within a complete
- Expertise in performance, power and area tradeoffs, NPU dataflows, workload mapping and system-level performance bottlenecks.
- Deep understanding of the ASIC design flow, including RTL design, SystemVerilog verification, synthesis, physical design and timing closure.
- Expertise in NPU compute architecture, tensor operations, numerical formats and efficient execution of AI workloads.
- Experience with compiler, runtime and hardware co-design for AI accelerators.
- Experience integrating accelerators with CPUs, NoC interconnects, DMA engines and coherent or non-coherent memory systems.
- Knowledge of SRAM and DDR memory hierarchies, bandwidth, caches, coherency and system-level quality of service.
- Understanding of electrical, thermal, power and clock constraints at the chip, package and system levels.
- Experience defining hardware-software interfaces, runtime and driver requirements, and NPU integration with SoC safety and security mechanisms.
- Proven ability to serve as a senior technical authority for complex semiconductor development initiatives, providing architectural guidance across multiple engineering disciplines and influencing critical technical decisions with senior engineering leadership and development partners.
- Experience evaluating competing architecture and technology approaches, resolving complex cross-domain technical tradeoffs, and presenting recommendations that balance performance, power, cost, feasibility, quality, and delivery objectives.
Desired Skills:- Experience with automotive-qualified AI compute or SoC designs.
- Experience with transformer and other neural-network inference workloads.
- Experience with automotive MCUs.
- Knowledge of Arm CPU platform architecture and accelerator integration.
- Experience with FPGA prototyping and pre-silicon emulation.
- Knowledge of SoC interfaces and protocols, including PCIe, Ethernet, CSI, I2C, SPI, DDR and non-volatile memory interfaces.
- Experience with secure boot, cryptography and hardware isolation.
- Automotive functional safety expertise and experience applying ISO 26262.
- SystemC or C++ modeling and performance-analysis experience.
Workplace Flexibility:- Travel to worldwide locations required
Years of Relevant Experience:- 15+ years of experience in SoC architecture and silicon development, including technical leadership of NPU or AI accelerator design and integration into a SoC.
Required Education:- Bachelor's Degree in Engineering
Desired Education: - Master's Degree in Engineering
CompensationSalary range is dependent on factors such as geographical differentials, credentials or certifications, industry-based experience, qualification and training. In the city of Mountain View, California the salary range for this position is $286,866 - $362,045.
CARIAD, Inc. provides performance based merits and annual bonus along with a competitive benefits package. Benefits include medical, dental, vision, 401k with employer match and defined contribution plan, short and long term disability, basic life and AD&D insurance, employee assistance program, tuition reimbursement and student loan repayment plans, maternity and non-primary caregiver leave, adoption assistance, employee referral program and vacation and paid holidays. We also offer a unique vehicle lease program that covers registration and insurance fees.
