5+ years of synthesis and STA experience on production tapeouts
Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus
Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints
Experience with logic equivalence checking (Formality or Conformal)
Strong Tcl and Python scripting
Responsibilities
Own logic synthesis and constraint development (SDC) for blocks and full chips
Drive timing closure across corners and modes, collaborating with RTL and physical design teams
Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis
Perform logic equivalence checking between RTL and netlist
Build automation to enhance synthesis and timing flows
Evaluate AI-generated constraints and timing fixes, defining quality standards
Benefits
Opportunity to work with leading semiconductor companies
Engagement with cutting-edge AI-assisted design tools
Collaborative environment with RTL and physical design teams
Focus on advanced technology nodes (7nm and below)
Potential for professional growth in a rapidly evolving field
Full Job Description
About this Role
You'll own the path from RTL to a timing-clean netlist. You'll close timing on real silicon programs with leading semiconductor companies while helping Voltai's AI learn to write constraints, diagnose violations, and close timing.
What You'll Do
Own logic synthesis and constraint development (SDC) for blocks and full chips.
Drive timing closure across corners and modes, working with RTL and physical design teams.
Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
Perform logic equivalence checking between RTL and netlist.
Build automation that makes synthesis and timing flows faster and more reliable.
Evaluate AI-generated constraints and timing fixes, and help define what good looks like.
What We're Looking For
5+ years of synthesis and STA experience on production tapeouts.
Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
Experience with logic equivalence checking (Formality or Conformal).
Strong Tcl and Python scripting.
Bonus Points
Advanced node experience (7nm and below).
Experience with ECO flows and timing signoff methodology.
