General Summary:As a member of the Qualcomm Si Process Packaging Solutions (PPS) team, this candidate will drive Si process technology evaluation, development, design enablement and productization for Mixed-Signal/RF products at foundry partners.
Responsibilities - Drive bulk Si and RFSOI technology evaluation, development and design enablement for RFFE designs, including RF switching and antenna circuits, receivers, transmitters.
- Work with Qualcomm design and product teams to define process and device requirements for continuous technology improvements.
- Define and execute test structures DOE, layout and characterization for process evaluation to meet design requirements.
- Design, simulate and test RF circuits to understand the process-design-layout interaction to guide process-design-layout optimization to achieve optimum performance.
- Interact with internal design teams, PDK teams, reliability, and product engineering to ensure technology support.
- Support Qualcomm design, layout, PTE and reliability teams to address their questions and resolve any device and design optimization issues.
- Assure product quality by devising testing methodology, and testing product and system capabilities.
- Work independently on assigned tasks with full ownership of technical execution and schedule commitments.
- Innovate new methods for continuous device and process improvement; support automation and AI-assisted workflows.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Preferred Qualifications:- Minimum of 8+ years of industrial experience developing advanced CMOS processes and devices
- Excellent understanding of the RF-CMOS, SOI or BiCMOS, process integration, reliability, design rules and best layout practices.
- Excellent understanding of PDK related details including DRC, LVS, LPE, etc.
- Proficiency in device level test-structure development, DOE design, statistical analysis, and data-driven problem solving
- Excellent understanding of sub-micron process/device optimization and its impact on digital/analog/RF/HV circuit design and product level performance is required. Experience designing wafer level designs (analog IPs, LNA, PAs) and circuit design flows is plus.
- Good knowledge of RF (e.g. S-parameters, Harmonics, Noise Figure) and DC characterization of devices on wafers, and in product ICs.
- Good knowledge of technology evaluation/benchmarking, SPC monitoring, and reliability qualification.
- Good understanding of BSIM, PSP-SOI device models and ability to run hardware correlations. Ability to tweak and update models is a plus.
- Fab device engineering or process integration experience preferably in RF devices is a plus.
- Foundry and OSAT interface experience is a plus.
- Good communication skills and demonstrated ability to meet deadlines and commitments.
Pay range and Other Compensation & Benefits: $145,600.00 - $218,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
