Role Overviewd-Matrix is looking for a Staff Analog Design Engineer to lead analog-mixed signal IC design for our next-generation AI inference accelerators. This role owns circuit design for two critical subsystems: our in-memory-compute engine and the die-to-die serial interface that enables scale-out. You will drive design from schematic through silicon bring-up, guiding layout engineers working in deep sub-micron process nodes (7nm and below) and ensuring designs meet low-power performance targets across process-voltage-temperature corners. You will partner closely with layout engineers, backend/digital integration teams, and cross-site colleagues to deliver silicon-ready designs. This is a high-impact role for someone who wants to shape the analog foundations of state-of-the-art AI hardware.
What You Will Do- Design analog-mixed signal circuits using industry-standard tools such as Cadence and Synopsys
- Develop schematic-level circuit designs and conduct system-level performance analysis
- Build test benches to support simulation and verification, including Monte Carlo yield analysis across PVT corners
- Guide layout engineers on circuit layout in deep sub-micron process nodes (7nm and below), including hands-on minor layout adjustments as needed
- Partner with backend engineers to integrate design and layout, and provide circuit models to support backend verification
- Support testboard design for silicon bring-up, bench debug, and characterization
- Build scripts to support silicon bring-up and test feature validation
What You Will Bring- BS, MS, or PhD in Electrical Engineering with 5+ years of related professional experience in high-speed circuit design (e.g., phase interpolators, clocking, PLL design)
- Experience with schematic capture, SPICE simulation, and Monte Carlo simulation
- Experience with circuit layout, extraction, and back-annotated simulation
- Experience with channel modeling using MATLAB or similar tools
- Strong cross-functional communication and collaboration skills, with the ability to work effectively across distributed, cross-site teams
- Strong analytical and problem-solving skills, with the ability to manage multiple priorities in a fast-paced environment
Preferred QualificationsWe'd be excited about candidates with deep expertise in any one of the following areas:
- SerDes verification & characterization - building/maintaining analog verification infrastructure (testbenches, regressions, Monte Carlo campaigns), migrating blocks across process nodes, or reliability analysis (EM, IR drop, ESD/latch-up)
- Clocking & CDR - ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon at 25 Gbps+ per lane, including bang-bang/baud-rate/DSP-assisted CDR architectures
- TX/RX datapath - high-speed driver or receive front-end design (CTLE, VGA, samplers), DFE/FFE equalization, or PAM4/DSP-based receiver architectures
- Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), familiarity with relevant specs (OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/7), or standards body participation
