DSP SW Engineer

E-Space

• $100K — $200K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 5+ years in DSP or digital communications
  • Proficient in C/C++ for algorithm implementation and debugging
  • Familiar with wireless PHY processing and 5G NR specifications
  • Understanding of fixed-point arithmetic and numerical precision
  • Experience with embedded software and hardware interfaces

Responsibilities

  • Implement DSP and 5G NR PHY functions for satellite communications
  • Run PHY/link-level simulations under satellite conditions
  • Develop and optimize C/C++ DSP firmware to meet specifications
  • Create test vectors and documentation for ASIC verification
  • Contribute to SystemC TLM and HLS development
  • Support pre-silicon verification and documentation of discrepancies

Benefits

  • Flexible working conditions suitable for high-impact projects
  • Opportunities to work on cutting-edge satellite communication technologies
  • Dynamic and fast-paced work environment
  • Engagement in innovative satellite design and manufacturing processes
  • Collaboration with experts in satellite component development
Full Job Description
What you will do:

  • Implement and evaluate defined DSP and 5G NR physical-layer (PHY) functions for satellite communications over non-terrestrial networks (NTN), working from agreed specifications and technical guidance.
  • Develop and run PHY/link-level simulations to measure error rates, throughput, and acquisition and tracking performance under representative satellite channel conditions, including propagation delay, Doppler, noise, and RF impairments.
  • Develop, test, and optimize C/C++ DSP firmware for 5G NR PHY processing, meeting defined execution-time, memory, power, and numerical-accuracy requirements.
  • Create floating-point and fixed-point reference models, reproducible test vectors, and expected results for ASIC designers and verification engineers. Document interfaces, scaling, rounding, saturation, and other assumptions needed to compare implementations.
  • Contribute to SystemC transaction-level modeling (TLM) and high-level synthesis (HLS) development, including synthesizable implementations, with guidance from engineers experienced in these flows.
  • Support pre-silicon verification and new-chip bring-up by running regressions, comparing model, firmware, and hardware results, investigating discrepancies, and documenting fixes with ASIC, verification, and software engineers.


What you bring to this role:

  • Demonstrated DSP and digital-communications fundamentals, including sampling, filtering, modulation, OFDM, synchronization, channel estimation, and error-correction concepts. Evidence may come from academic, research, personal, or professional projects.
  • Ability to implement and debug numerical algorithms in C/C++, and to use Python or MATLAB for simulation, analysis, and test automation.
  • Working knowledge of wireless PHY processing and the ability to translate technical specifications into implementation and test cases; familiarity with the basic structure of a 5G NR PHY.
  • Understanding of fixed-point arithmetic, quantization, overflow, and numerical precision, with the ability to compare an implementation against a reference model.
  • Understanding of embedded software constraints, including execution time, memory use, and hardware/software interfaces, supported by practical implementation or debugging work.
  • Ability to build reproducible tests, use version control, document technical assumptions and results, and explain discrepancies during code and design reviews.


Bonus points for the following:

  • Experience with SystemC TLM, or with HLS tools to develop and verify synthesizable C/C++ or SystemC implementations.
  • Experience with 5G NR or NTN algorithms and specifications, satellite channel modeling, or compensation for Doppler and timing effects.
  • Experience with FPGA/ASIC verification, emulation, SDR platforms, chip bring-up, or laboratory validation of communication systems.
  • Experience with 5G NR MAC, PHY/MAC interfaces, scheduling interactions, or HARQ procedures.
  • Experience implementing and optimizing algorithms on vector DSPs, including SIMD intrinsics, vectorization, and efficient memory access.
  • Experience with low-power ASIC or firmware design, including reducing computation and data movement, managing idle states, or measuring power consumption.


Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.

$100,000 - $200,000 a year

This is a full time, exempt position, based out of our Santa Clara office. The target base pay for this position is $100,000 - $200,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience.

We are redefining how satellites are designed, manufactured and used-so we're looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that's your experience - then we'll be immediately wow-ed.

E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

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