Sr. Technology Development Engineer

Monolithic Power Systems, Inc.

$120K — $150K *
Technical Services
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Master’s or Ph.D. in Electrical Engineering or equivalent
  • 3+ years of experience in analog process and device development for Master's degree holders
  • Familiarity with Bipolar, CMOS, DMOS and high voltage devices
  • Solid understanding of semiconductor device physics and process/device simulation
  • Proficiency in design rules and spice model extraction, as well as experience with graphics layout software and mask making requirements.

Responsibilities

  • Develop and maintain MPS power IC devices and processes
  • Collaborate with MPS Foundry Group and fabrication personnel for device development
  • Define and verify design rules in coordination with CAD group
  • Clarify and document device requirements with Design group
  • Coordinate device layout and tooling needs with Mask Design Group
  • Consult with Product Engineering and Foundry Group on yield questions
  • Engage in semiconductor device design, process simulation, and test structure layout.
Full Job Description
Job Description: Responsible for maintaining and developing MPS power IC devices and processes. Essential Functions:
  • Process and device development for DMOS, Bipolar, CMOS, high voltage devices
  • Interface with MPS Foundry Group and with fabrication foundry personnel for development and qualification of devices, processes, and process changes.
  • Define design rules for various analog process technologies, and verify design rules vs. DRCs (Design Rule Checks) with CAD group.
  • Interface with Design group to provide, clarify, and document device requirements and capabilities.
  • Interface with Mask Design Group and Mask Shop for device layout and for mask/reticle tooling requirements.
  • Interface and consult with Product Engineering and Foundry Group to yield questions.
  • Engaged in:
    • Semiconductor device design to meet electrical specifications.
    • Process and device simulation.
    • Test structure layout using CAD software.
    • Definition of process experiments
    • Electrical measurements at wafer level
Qualifications:
  • Master’s or Ph.D. Degree in Electrical Engineering or equivalent
  • Master’s with 3+ years experience or Ph.D in analog process and device development
  • Familiarity with Bipolar, CMOS, DMOS, high voltage devices
  • Knowledge of semiconductor device physics, process and device simulation, design rules, spice model extraction, graphics layout software and mask making requirements.
Locations:
  • San Jose, CA

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