Descriptions & Requirements

Job Description and Requirements

This role offers an opportunity to lead innovation in semiconductor product engineering while driving the development of next-generation NVM/OTP IP products.

You Are

As a Sr. Staff Product Engineer, you will lead the silicon validation of non-volatile memory/one-time programmable (NVM/OTP) intellectual property (IP) and associated blocks (analog circuits, power supplies, programming controllers, access ports/wrappers, and Built-In Self-Test (BIST) blocks).

You will provide technical leadership in test plan creation, programming algorithm development, data analysis and modeling, test optimization, and failure analysis. You will collaborate closely with cross-functional teams to complete Design Validation, Characterization, and Qualification test reports for NVM/OTP IP products.

What You'll Be Doing

* Lead the silicon validation effort for NVM/OTP IP products through Design Validation, Characterization, and Qualification phases.
* Define test coverage strategies for critical device functions and parameters, ensuring robust DC and AC characterization with optimized guard-banding techniques.
* Investigate and resolve complex functional and reliability issues, oversee silicon performance analysis, and drive root-cause failure analysis (FA) projects.
* Develop scripts to automate workflows, perform statistical analysis and data visualization, build performance and reliability models, and generate test reports.
* Drive continuous improvements in test efficiency and quality, DOE methodology, data analysis, and cost reduction through AI, innovation and automation.
* Collaborate with external test/reliability labs to complete test data collection and qualification (HTOL/HTSL) testing.

What You'll Need

* BS or MS in Electrical Engineering (preferred), Engineering Physics, Computer Science, or a related field.
* 8+ years of hands-on experience in semiconductor product/test engineering, with a strong background in NVM products.
* Experience with data analysis tools such as Spotfire, Minitab or JMP.
* Knowledge of memory fault models and advanced test methodologies for defect detection and reliability analysis.
* Experience with semiconductor test lab equipment: memory ATE testers (Credence Kalos 2 preferred), automated handlers, oscilloscopes, waveform analyzers, and micro-probing stations.
* Proficiency with scripting languages such as Python or Perl, with knowledge of memory pattern algorithm development for ATE MTO/ALPG hardware.
* Excellent communication and documentation skills, with a track record of mentoring engineers and collaborating across engineering teams.
* Experience in optimizing test efficiency, semiconductor data analysis, and writing silicon test reports.
* Strong analytical and problem-solving skills, with a proactive approach to resolving silicon debug and validation challenges.

The Impact You Will Have

* Your test plans will define how Synopsys qualifies and ships NVM and OTP IP that ends up in millions of devices, directly affecting product quality and time to market
* The programming algorithms and test methodologies you develop will become the foundation for how the team validates future memory IP generations
* Your failure analysis work will catch design issues early, saving months of respins and preventing costly field failures downstream
* The automation and scripting you build will free up engineering time across the validation team, letting them focus on harder problems instead of manual data wrangling
* Your mentorship will shape how junior engineers approach silicon debug, test coverage, and data-driven decision making
* The reliability models you create will inform design tradeoffs and customer qualification requirements, giving product teams the data they need to make confident decisions
* Your collaboration with external labs will ensure qualification testing stays on schedule and meets the rigor that Synopsys IP customers expect

Who You Are

* You can walk into a lab, look at a failing part, and start forming hypotheses about what is wrong based on the pattern of failures across voltage, temperature, and time
* You write test reports that engineers and product managers can actually understand, translating complex characterization data into clear conclusions and actionable recommendations
* You mentor without being asked, you see a junior engineer struggling with a debug approach and you pull them aside to show them a better way
* You push back when a test plan is too thin or a schedule does not leave room for proper characterization, and you do it in a way that builds trust instead of friction
* You stay organized across multiple silicon lots, test phases, and FA projects without dropping threads or losing track of what needs to close before tape-out
* You are comfortable presenting technical tradeoffs to senior engineers and management, explaining why a particular guard band or test coverage decision matters in terms they care about

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#LI-DP1

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.