Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
7-10 years of relevant physical design experience (RTL-to-GDS or netlist-to-GDS) on ASICs; FPGA P&R experience a plus
Hands-on experience with industry PD tools (e.g., Innovus, ICC2/Fusion Compiler, PrimeTime, Calibre or equivalent)
Proven timing closure, CTS, and physical verification on multi-clock, high-utilization designs
Scripting (Tcl/Python) and ability to debug tool and design issues independently
Demonstrated ability to work with front-end and DFT to meet system performance goals
Responsibilities
Execute physical design for DSP, beamforming, and interface partitions; manage floorplan, power, placement, CTS, routing, and optimization
Close timing with PD tools in partnership with the synthesis/timing owner; implement timing and functional ECOs
Integrate memories, I/Os, high-speed interfaces, and DFT structures; manage congestion and utilization on high-throughput datapaths
Run physical verification (DRC/LVS/antenna) and support EM/IR sign-off
Collaborate with RTL, synthesis/STA, and DFT on constraints, scan timing, and design changes affecting layout
Support FPGA P&R and timing when prototypes are used before or alongside ASIC
Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows
Benefits
Opportunity to shape product differentiation and impact PPA
Work in a collaborative environment with early senior digital hires
Engage in end-to-end design processes from floorplan to sign-off
Potential for career growth and mentoring opportunities as the team expands
Involvement in cutting-edge technology related to phased-array solutions
Full Job Description
The Role
We're looking for a Senior Physical Design Engineer who can own block- and chip-level implementation from netlist to GDS (and FPGA P&R support) for our phased-array solutions. As one of our early senior digital hires, you will floorplan, place, clock, route, and sign off the silicon that carries digital beamforming and adaptive processing-bridging synthesis to a manufacturable, timing-clean layout.
You'll work end-to-end: floorplan and power grid, placement, CTS, routing, extraction, STA collaboration, physical verification, EM/IR, ECOs, and lab support. The decisions you make will directly shape PPA, schedule, and product differentiation.
Responsibilities
Execute physical design for DSP, beamforming, and interface partitions and for top level: floorplan, power, placement, CTS, route, optimization
Close timing with PD tools in partnership with the synthesis/timing owner; implement timing and functional ECOs
Integrate memories, I/Os, high-speed interfaces, and DFT structures; manage congestion and utilization on high-throughput datapaths
Run physical verification (DRC/LVS/antenna) and support EM/IR sign-off
Collaborate with RTL, synthesis/STA, and DFT on constraints, scan timing, and design changes that affect layout
Support FPGA P&R and timing when prototypes are used before or alongside ASIC
Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
7-10 years of relevant physical design experience (RTL-to-GDS or netlist-to-GDS) on ASICs; FPGA P&R experience a plus
Hands-on experience with industry PD tools (e.g., Innovus, ICC2/Fusion Compiler, PrimeTime, Calibre or equivalent)
Proven timing closure, CTS, and physical verification on multi-clock, high-utilization designs
Scripting (Tcl/Python) and ability to debug tool and design issues independently
Demonstrated ability to work with front-end and DFT so implementation matches system performance goals
Preferred Qualifications
MSc or PhD in EE/CE or a related field
Tape-out experience and post-silicon or FPGA validation support
Background in communications (5G/6G, satellite) or radar / phased-array ASICs
Familiarity with high-speed interfaces, low-power design, and Cadence/Synopsys full flows
Prior work on phased-array or multi-antenna systems from concept through fielded product
