Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
7-10 years of experience in digital signal processing and digital RTL design for ASICs or FPGAs
Proficient in MATLAB and/or Python for algorithm design and simulation
Hands-on experience with SystemVerilog/Verilog RTL, including synthesis and timing closure
Strong foundation in DSP fundamentals and real-time hardware implementation
Responsibilities
Develop DSP algorithms for digital beamforming and adaptive nulling
Own algorithm architecture from high-level models to fixed-point design
Design and implement digital RTL for DSP datapaths and control logic
Drive RTL designs through synthesis and timing analysis
Define performance requirements and optimize hardware architecture
Perform system-level simulations to assess algorithm impact
Support lab validation and iterative refinement of algorithms and RTL
Benefits
Opportunity to shape system capability and product differentiation
Work on cutting-edge phased array solutions
Collaborative environment with potential for mentorship
Involvement in technical strategy and design reviews
Access to advanced tools and technologies in signal processing
Full Job Description
The Role
We're looking for a Senior DSP / RTL Engineer who can own both the signal processing algorithms and their efficient digital implementation for our phased array solutions. As one of our early senior digital hires, you will define processing architecture, develop beamforming and adaptive algorithms, and implement key blocks in RTL-bridging the gap from concept to silicon/FPGA.
You'll work end-to-end: algorithm design and modeling, fixed-point conversion, RTL coding and synthesis, timing closure, and lab validation. The decisions you make will directly shape system capability and product differentiation.
Responsibilities
Develop and refine DSP algorithms for digital beamforming, adaptive nulling, channel estimation, calibration, and interference mitigation in communications and radar phased arrays
Own algorithm architecture from high-level floating-point models (MATLAB/Python) through fixed-point design, quantization analysis, and bit-true modeling
Design and implement digital RTL (SystemVerilog/Verilog) for DSP datapaths, control logic, beamforming engines, high-speed interfaces, and supporting blocks
Drive RTL designs through synthesis, timing analysis, lint/CDC checks, place-and-route support, and silicon/FPGA validation
Define performance requirements and hardware architecture trade-offs (throughput, latency, area, power); optimize implementations for efficient resource utilization
Perform system-level simulations and link analyses to quantify algorithm and implementation impact on overall array performance (SINR, EVM, detection range, etc.)
Support lab bring-up, debug, and iterative refinement of algorithms and RTL on FPGA/ASIC prototypes based on measured data
Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
7-10 years of relevant experience spanning digital signal processing algorithm development and digital RTL design for ASICs or FPGAs
Strong proficiency with MATLAB and/or Python for algorithm design, simulation, and fixed-point analysis
Proven hands-on experience writing production-quality SystemVerilog/Verilog RTL, including synthesis, timing closure, lint, and CDC analysis
Solid foundation in DSP fundamentals: multi-rate processing, adaptive filtering, array signal processing, estimation theory, and numerical considerations for fixed-point arithmetic
Demonstrated ability to translate algorithms into efficient real-time hardware implementations
Preferred Qualifications
MSc or PhD with a focus on signal processing, communications, VLSI, or radar systems
Direct experience with digital beamforming, adaptive arrays, MIMO processing, or space-time adaptive processing (STAP)
Background in communications (e.g., 5G/6G, satellite) or radar system requirements and performance metrics
Experience taking designs from algorithm through RTL, synthesis, timing closure, and post-silicon or FPGA validation
Familiarity with high-speed interfaces, AXI/APB buses, low-power design techniques, and industry-standard EDA tools (Cadence/Synopsys)
Prior work on phased-array or multi-antenna systems from concept through fielded product
This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.
