Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
7-10 years of relevant DFT experience on ASICs or large FPGAs
Hands-on experience with industry DFT tools (e.g., Siemens Tessent, Synopsys TestMAX)
Proven ability to verify DFT in simulation and take patterns to silicon or FPGA
Solid understanding of RTL (SystemVerilog/Verilog) and test-mode constraints
Demonstrated ability to work across RTL, synthesis, PD, and test engineering
Responsibilities
Define and implement hierarchical and full-chip DFT architecture for digital beamforming and adaptive blocks
Insert, verify, and sign off DFT structures; drive coverage and pattern quality
Generate and validate ATPG patterns; optimize pattern count and test power
Run and debug gate-level simulations of test modes; support FPGA/ASIC bring-up
Partner with RTL, synthesis, and physical design to ensure timing integrity
Automate DFT flows using Tcl/Python; manage specs and coverage reports
Contribute to technical strategy, design reviews, and mentoring
Benefits
Opportunity to shape the test architecture for cutting-edge technology
Work in a collaborative environment with early senior digital hires
Engage in end-to-end DFT processes from architecture to production
Contribute to the development of advanced phased-array ASIC and FPGA solutions
Potential for career growth as the team expands
Full Job Description
The Role
We're looking for a Senior DFT Engineer who can own Design-for-Test from architecture through ATPG, silicon bring-up, and production test for our phased-array ASIC and FPGA solutions. As one of our early senior digital hires, you will define the test architecture that makes complex beamforming and adaptive-processing silicon manufacturable, diagnosable, and field-reliable-bridging RTL to ATE and first silicon.
You'll work end-to-end: DFT architecture, scan/BIST insertion, pattern generation, gate-level verification, timing/test-mode constraints with synthesis and PD, and lab/ATE validation. The decisions you make will directly shape yield, test cost, and product quality.
Responsibilities
Define and implement hierarchical and full-chip DFT architecture for digital beamforming, adaptive, and high-speed interface blocks (scan, compression, MBIST/repair, LBIST, JTAG / IEEE 1149.1/1500/1687, on-chip debug)
Insert, verify, and sign off DFT structures; drive coverage, DRC, and pattern quality
Generate and validate ATPG patterns (stuck-at, transition, and other required fault models); optimize pattern count, test time, and test power
Run and debug gate-level simulations of test modes; deliver vectors and support FPGA/ASIC bring-up and ATE
Partner with RTL, synthesis/timing, and physical design so scan and test clocks close timing and do not break PPA
Automate DFT flows (Tcl/Python); own specs, coverage reports, and silicon diagnosis notes
Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
7-10 years of relevant DFT experience on ASICs or large FPGAs
Hands-on experience with industry DFT tools (e.g., Siemens Tessent, Synopsys TestMAX) including scan insertion, compression, MBIST, and ATPG
Proven ability to verify DFT in simulation and take patterns to silicon or FPGA
Solid understanding of RTL (SystemVerilog/Verilog), STA/test-mode constraints, and CDC/lint implications of DFT logic
Demonstrated ability to work across RTL, synthesis, PD, and test engineering
Preferred Qualifications
MSc or PhD in EE/CE or a related field
Tape-out and post-silicon DFT bring-up, yield, or diagnosis experience
Background in communications (5G/6G, satellite) or radar phased-array SoCs
Familiarity with high-speed interfaces, AXI/APB, low-power test techniques, and Cadence/Synopsys implementation tools
Prior work taking a phased-array or multi-antenna product from concept through fielded silicon
This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.
