BS/MS in Electrical Engineering, Computer Engineering, or related field with 7+ years in RTL and functional verification using SV/UVM.
Experience with PCIe verification, gate-level simulation, and firmware-based simulation.
Proficient in RTL design and computer architecture concepts.
Strong debugging, problem-solving, and analytical skills.
Preferred: Background in high-speed connectivity solutions (PCIe/CXL, SerDes, optical DSP).
Preferred: Experience working across HW/SW boundaries with application engineering/firmware teams.
Preferred: PHY verification experience.
Responsibilities
Understand design intent and develop comprehensive verification and test plans.
Develop reusable, scalable SV-UVM testbenches and write test sequences.
Verify PCIe subsystems and other interfaces at block and subsystem levels.
Write assertions, checkers, and coverage; analyze functional and code coverage gaps.
Build firmware-based simulations in C to validate HW/SW interactions and debug silicon failures.
Automate flows using Python/Perl/Shell scripting; collaborate with AEs and FW teams on debug and feature implementation.
Benefits
Discretionary bonus eligibility.
Equity options.
Full range of medical benefits.
Full Job Description
Job description
Team Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Base salary range is $138,000 - $218,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.
Qualifications
Basic Qualifications
BS/MS in Electrical Engineering, Computer Engineering, or a related field, with seven or more years of experience in RTL and functional verification using SV/UVM.
PCIe verification experience, plus experience with gate-level simulation and firmware-based simulation.
Proficiency in RTL design and computer architecture concepts.
Strong debugging, problem-solving, and analytical skills.
Preferred Qualifications
Background in high-speed connectivity solutions (PCIe/CXL, SerDes, optical DSP).
Experience working across HW/SW boundaries and with application engineering/firmware teams.
PHY verification experience.
Job responsibilities
Understand design intent and develop comprehensive verification and test plans; develop reusable, scalable SV-UVM testbenches and write test sequences.
Verify PCIe subsystems and other interfaces (I2C/I3C/SMBus/CPU/UART/SPI) at block and subsystem levels (e.g., PHY, controller).
Write assertions, checkers, and coverage, analyze functional and code coverage gaps, and drive closure.
Build firmware-based simulations in C that mirror or approximate real FW behavior to validate HW/SW interactions; reproduce silicon failures in simulation and perform deep debug to root cause.
Automate flows with Python/Perl/Shell scripting; collaborate with AEs and FW teams on debug, feature implementation, and spec contributions driven by DV findings.
