Summary of Role: Seeking a Senior System-on-Chip Design Verification engineer to verify the High-Performance Automotive Microcontrollers. The candidate will be responsible for contributing to all phases of the verification lifecycle, including reviewing specifications, developing testbench architecture, creating testplans, defining and closing coverage, and debugging failing simulations.
Essential Responsibilities:- Hands-on development of testbenches, testcases and checkers to exercise and measure design behavior against specified intent.
- Debug differences in simulated behavior of designs and design specifications.
- Contribute to the development of DV flows and methodology for improved development efficiency.
- Independently manage verification tasks while mentoring junior team members.
- Collaborate with cross-functional teams (Spec, Design, etc) to resolve bugs.
Other Responsibilities:- Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications:- Bachelor's degree in Electrical/Computer Engineering, Computer Science, or related field
- 5-8 years of experience in SoC verification.
- Expertise in writing tests using SystemVerilog, UVM and C.
- Experience with scripting languages like Python, Tcl/Tk, Perl.
- Understanding of SOC interconnects and bus standards such as AXI, AHB, APB.
- Excellent analytical and problem-solving skills.
- Proven written and verbal technical communication skills.
- Self-motivated, collaborative team player able to broadly contribute project goals.
- Innovative approach to improving existing processes and methodologies.
Preferred Qualifications- Master's degree in Electrical/Computer Engineering, Computer Science, or related field
- Experience with RISC-V, ARM and/or MIPS CPU architectures.
- Knowledge of register description languages (IP-XACT, SystemRDL, UVM RAL).
- Familiarity with Functional Safety standards (ISO 26262) and fault injection methodologies.
- Background with power-aware (UPF) and gate-level simulations (GLS)
- Familiarity of formal verification tools and techniques.
Expected Salary Range$106,000.00 - $184,000.00
The exact Salary will be determined based on qualifications, experience and location.
