Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
3+ years of RTL-to-PD implementation experience with successful tapeout experience.
Proficiency in SystemVerilog/Verilog and familiarity with Cadence/Synopsys toolchains.
Strong ability in static timing analysis and writing timing constraints from RTL designs.
Experience in developing automated design flows and knowledge of AI-assisted automation tools.
Responsibilities
Own RTL-to-PD handoff flows to partners, ensuring designs meet performance and quality targets.
Drive timing closure by managing timing constraints and resolving setup violations across designs.
Execute floorplanning and physical implementation using tools to optimize PPA.
Build and maintain automated design flows to streamline synthesis and analysis processes.
Collaborate with design, DFT, and verification teams to ensure seamless integration and quality checks.
Contribute to post-DV activities including power analysis and formal verification as required.
Benefits
Competitive salary and benefits package
Flexible PTO
401k
Full Job Description
What you'll do:
As a Persimmons Silicon Design Engineer, you will be responsible for high quality RTL drops to our PD Partners of next-generation AI silicon. Your primary duties and responsibilities include:
Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.
Lead unit level design execution & verification planning. Collaborate with architecture, software, and design teams to develop MAS, execution & test plans that ensures we meet SoC specifications.
Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi-corner environments.
Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.
Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes-leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.
Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.
Contribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.
Requirements
What You Bring To The Table:
Educational Foundation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Proven Experience: 3+ years of hands-on RTL-to-PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.
Experience with MAS & test plan development, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs.
Strong skills in SystemVerilog, Verification methodology, and C/C++ embedded code for processors validation.
Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign-off checks.
Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL-level design understanding.
Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI-assisted automation tools is a strong plus.
Demonstrated fluency with modern AI tools and workflows (e.g., leveraging AI assistants for research, analysis, or productivity).
