Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; Master's preferred
7+ years of experience in implementing DSP or communications algorithms in RTL and/or embedded C
Strong fundamentals in DSP and digital communications, including modulation and FEC
Experience with fixed-point conversion and bit-true implementation from MATLAB/Simulink
Proficient in FPGA design flow, including simulation and timing closure
Experience in building testbenches and verifying against golden reference models
Responsibilities
Implement modem and physical-layer blocks from MATLAB/Simulink models into RTL and embedded C
Own fixed-point conversion, analyzing quantization and precision trade-offs
Build accurate testbenches to verify RTL and C implementations
Optimize FPGA timing and resource utilization on Xilinx/AMD or Intel FPGAs
Partition signal chain between FPGA fabric and embedded processor
Debug physical layer on captured and live signals with cross-functional teams
Benefits
Highly competitive equity grants
Opportunities for professional development
Collaborative work environment
Access to cutting-edge technology
Potential for career advancement within the company
Full Job Description
What you will be doing
As a Senior Wireless Engineer, you will turn our modem and waveform designs into real, deployable hardware. Working directly under our Senior Wireless Systems Engineer II, you will take MATLAB/Simulink models of the physical layer and implement them as bit-true, fixed-point designs in C and RTL for our FPGAs and SoCs. You will own fixed-point conversion, verification against the golden reference, and FPGA timing and resource optimization - getting real waveforms onto our drones and working over the air.
Responsibilities
Implement modem and physical-layer blocks - modulation/demodulation, synchronization, equalization, and channel coding/FEC - from MATLAB/Simulink models into RTL (Verilog/VHDL) and embedded C
Own fixed-point conversion from floating-point models, analyzing quantization, precision, and dynamic-range trade-offs
Build bit- and cycle-accurate testbenches that verify RTL and C implementations against the MATLAB/Simulink golden reference
Close timing and optimize LUT, DSP, and BRAM utilization on Xilinx/AMD (or Intel) FPGAs and SoCs
Partition the signal chain between FPGA fabric and embedded processor, co-designing the hardware/software boundary
Debug the physical layer on captured and live signals alongside the communication systems, RF, and firmware teams, working directly with the Principal Communications Systems Engineer to take waveforms from model to silicon
You should have the following
Bachelor of Science in Electrical Engineering, Computer Engineering, or a related field required; Master's degree highly preferred
7+ years implementing DSP or communications algorithms in RTL (Verilog/VHDL) and/or embedded C for FPGA or SoC targets
Strong DSP and digital communications fundamentals: modulation, synchronization, equalization, filtering, and FEC/channel coding
Demonstrated experience with fixed-point conversion and bit-true implementation from MATLAB/Simulink models
Proficiency with the FPGA design flow: simulation, synthesis, timing closure, and resource optimization (Vivado/Vitis or Quartus)
Experience building testbenches and verifying implementations against a golden reference model
Nice to have
Model-Based Design: Generating or hand-optimizing HDL and C from Simulink using MATLAB HDL Coder and Embedded Coder
Wireless Modems: Hands-on implementation of an end-to-end modem (OFDM, spread spectrum, or single-carrier) that shipped in hardware
SoC Integration: Zynq, RFSoC, or similar SoCs, including AXI interfaces and hardware/software co-design
RF/SDR Familiarity: Understanding of the RF front-end, data converters (ADC/DAC), and software-defined radio pipelines
Advanced FEC: Hardware implementation of LDPC, Turbo, Viterbi, or Reed-Solomon decoders
US Salary Range
$187,000 - $261,500 USD
The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.
