Senior Modem SOC Design Engineer - TeraWave

Application close date:

Blue Origin is pioneering the future of space-basedconnectivitywithTeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6Tbpsanywhere on Earth.This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations.

As a Senior Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will design digital hardware for the TeraWave satellite communication System on Chip (SOC). You will own RTL design for modem datapath and PHY blocks, implement signal processing hardware, and build out the Arm compute subsystem, debug, and IO infrastructure that surround it. This is an individual contributor role with no direct reports. You will work from communication system specifications through microarchitecture, RTL, SOC integration, and timing closure, partnering with architecture, verification, and physical design teams to deliver production silicon.

Responsibilities

• Design RTL in Verilog or System Verilog for modem datapath and PHY blocks
• Define microarchitecture from satellite communication system specifications and performance requirements
• Implement signal processing hardware including filters, FFT, equalizers, and forward error correction
• Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration
• Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure
• Design general purpose IO subsystem logic and associated configuration register interfaces
• Integrate subsystem and SOC level blocks including clock and reset architecture
• Support synthesis, timing constraint development, and timing closure with physical design teams

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• Minimum 5 years of experience in digital ASIC or SOC RTL design
• Experience with RTL design in Verilog or System Verilog for modem or PHY blocks
• Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers
• Experience implementing signal processing hardware such as filters, FFT, or forward error correction

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related technical field
• Experience with debug subsystem design using Arm CoreSight components
• Experience defining microarchitecture from communication system and algorithm specifications
• Experience with SOC level integration including bus fabric, clock, and reset architecture
• Experience with synthesis, timing constraint development, and timing closure support
• Experience with LPDDR6 or other high speed memory interface subsystems
• Experience with gigabit Ethernet or 25G high speed serial interface subsystems

Base Pay Range for:

Other site ranges may differ

Benefits

• Benefits include:  Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off:  Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.