The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.
We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat:
- Find critical silicon issues earlier - often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role.
- Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies.
What you'll be doing:- Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA's GPU, SoC, and CPU programs.
- Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready.
- Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation.
- Develop new strategies to keep programs on milestone when upstream dependencies - software, firmware, methodology, validation - slip.
- Hire, mentor, and retain senior technical talent. Build a strong bench and grow individual contributors into the next generation of senior technical leaders.
- Partner across architecture, design, DFT, software, firmware, QA, and manufacturing teams.
- Build operational rigor - bring-up tracking, debug forums, and a clear translation of execution data into structured, decision-ready options.
What we need to see:- Bachelor's or Master's in Electrical or Computer Engineering (or equivalent experience), plus over 12+ overall years of system-level post-silicon bring-up and debug experience, including 5 years leading technical teams, with shipped silicon.
- Direct experience finding critical silicon issues before software was production-ready - including building or scaling wide-area or in-system test programs that ran in production.
- Led technical teams across multiple geographies, with clear examples of attracting, growing, and retaining senior technical talent.
- Strong EE fundamentals across DFT, digital design, computer architecture, power, timing, and fault analysis, plus the ability to translate complex technical issues into clear options for executive audiences.
Ways to stand out from the crowd:- A history of process and methodology improvements that meaningfully lifted bring-up velocity, debug efficiency, or shipped silicon quality on programs you led.
- Experience partnering deeply with a counterpart team in India or another major engineering hub - examples of building shared culture, shared metrics, and shared on-call across geographies.
- DFT experience with system-test features for in-field test on production silicon, plus familiarity with fault models, DPPM, quality metrics, and RAS.
- Concrete examples of redesigning how a team works with AI - faster analysis, smarter debug, automated reporting, or workflows the team adopted broadly.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 232,000 USD - 368,000 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 29, 2026.
This posting is for an existing vacancy.
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