About the Engagement The I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem. You will collaborate with architecture, RTL, verification, firmware, physical design, and IP partners. Client identity and detailed program specifications are shared under confidentiality during interviews.
About the PositionYou will establish and execute verification plans for assigned blocks, subsystems, and chip-level functions. Working closely with designers and architects, you will turn requirements into measurable verification goals and produce the evidence needed for sign-off, covering both high-speed datapaths and firmware-controlled management functions.
Key Responsibilities- Build verification plans that map requirements to test scenarios, platforms, coverage goals, and sign-off criteria.
- Develop reusable SystemVerilog/UVM environments, sequences, agents, scoreboards, reference models, and assertions.
- Integrate vendor VIP and models; verify configured IP and end-to-end connectivity across protocol and PHY interfaces.
- Verify legal static-switch mappings, protocol modes, data integrity, latency, throughput, and reset or recovery behavior.
- Verify CSR access, boot and configuration sequences, sideband management, interrupts, and error handling with firmware teams.
- Apply simulation, formal and connectivity checks, low-power verification, and hardware/software co-simulation where appropriate.
- Automate regressions, triage failures, and close functional, assertion, and code coverage with documented exclusions.
- Review CDC/RDC findings with designers, support gate-level sanity checks and bring-up, and report verification readiness.
Must-Have Qualifications- Extensive hands-on ASIC verification experience, 10 years or more, with ownership through tape-out sign-of.
- Strong SystemVerilog and UVM skills, including constrained-random stimulus and reusable testbench architecture.
- Proven ability to write verification plans, define coverage, debug complex failures, and drive closure.
- Experience verifying high-speed interfaces, complex SoCs, networking ASICs, or die-to-die interconnect.
- Hands-on VIP integration, reference modeling, scoreboarding, and assertion-based verification.
- Understanding of multi-clock and reset behavior, protocol corner cases, and the limits of simulation and static checks.
- Strong scripting and regression automation skills, with disciplined test and configuration management.
- Ability to work independently, review others' work, and explain remaining risks and sign-off evidence clearly.
Nice-to-Have- UCIe, PCIe Gen6/Gen7, Ethernet PCS/FEC, or 224G SerDes and mixed-signal IP verification.
- Formal model checking, connectivity verification, or power-aware simulation with UPF.
- Embedded processor verification, secure boot, AXI/APB, register models, or firmware-driven testing.
- FPGA prototyping or emulation, silicon bring-up, and reviewed AI-assisted verification workflows.
Work ArrangementOttawa, Canada, is preferred. Hybrid arrangements may be considered based on the candidate and project needs. Clear written communication, independent execution, and collaboration with distributed engineering teams are essential.
CompensationCompensation will reflect individual experience, technical capability, and the responsibilities of the role. The package will be discussed during the recruitment process.
Only candidates selected for an interview will be contacted.
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