Senior FPGA Design Engineer

Senior FPGA Design Engineer The Reconfigurable Computing Group at ISI develops computer architectures and design methods that make specialized hardware more adaptable, efficient, and trustworthy. Recent work combines FPGA prototyping, ASIC design, purpose-built electronic design automation tools, and hardware-software co-design to advance rapidly reconfigurable processing for RF sensing and communications, acceleration of fully homomorphic encryption, and hardware security and assurance. The group builds and evaluates working systems, develops the tools needed to program and verify them, and collaborates across disciplines to move research toward operational use. We are seeking a highly talented and motivated Senior FPGA Design Engineer to research and develop novel tools and techniques for assuring FPGA hardware. Working with research staff and technical collaborators, the engineer will plan and execute specialized FPGA designs to assess device functionality and state; work directly with FPGA hardware and laboratory instrumentation to measure, validate, and analyze device characteristics; and identify, plan, and implement methods that extend commercial and open-source EDA tools with new assurance capabilities. This position is based in Arlington, VA. Hybrid work options are available Job Responsibilities 3 Plan, lead, implement, and verify specialized FPGA systems and RTL components in VHDL or Verilog to support hardware-assurance research. 3 Use FPGA EDA tools to perform synthesis, implementation, timing analysis, timing closure, and device programming. 3 Interface directly with FPGA hardware, power supplies, and other test instrumentation to collect measurements, validate behavior, and analyze device functionality and characteristics. 3 Develop Python, TCL, and related scripts to automate design flows, testing, data collection, and analysis. 3 Identify, plan, and implement extensions to commercial and open-source EDA tools, and evaluate new FPGA-assurance capabilities. 3 Translate research concepts and project goals into technical plans, implemented prototypes, and independently developed system components, working under minimal supervision. 3 Document designs, methods, test results, and technical progress; contribute to sponsor reports, publications, presentations, and meetings with collaborators. 3 Review technical implementations, establish engineering best practices, provide technical mentorship, and guide junior researchers and engineers as needed. 3 Stay current with FPGA architectures, EDA methods, hardware-assurance research, and emerging AI-assisted design approaches relevant to project goals. Minimum Qualifications 3 Masters degree in computer engineering, electrical engineering, computer science, or a closely related field. 3 Eight or more years of overall relevant research engineering experience, including at least five years of directly relevant FPGA design experience. 3 Demonstrated experience planning and executing FPGA designs and developing RTL in VHDL or Verilog. 3 Proficiency with scripting languages such as Python or TCL. 3 Proficiency with FPGA EDA tools such as AMD Xilinx Vivado or Intel Altera Quartus, including synthesis, implementation, and timing closure. 3 Experience interfacing directly with FPGA hardware, power supplies, and other test instrumentation. 3 Willingness and eligibility to apply for and maintain a Top Secret security clearance. Eligibility for this clearance requires U.S. citizenship. Preferred Qualifications 3 Ten or more years of relevant research engineering experience. 3 Current Secret security clearance or higher. 3 Experience applying large language model assisted design to FPGAs or implementing AI or machine learning workloads on FPGAs using AMD Vitis AI or Intel Altera FPGA AI Suite. 3 Knowledge of FPGA architecture and device primitives, including AMD Xilinx Zynq, Virtex-7, UltraScale+, or Versal devices, or comparable Intel Altera devices. 3 Contributions to or experience with open-source EDA tools such as Google Project X-Ray, VTR or VPR, RapidSmith, or TORC. 3 Demonstrated use of revision-control systems such as Git or Mercurial in a multi-user project environment. The annual base salary range for this position is $140,000 to $170,000.When extending an offer of employment, the University of Southern California considers factors such as, but not limited to, the scope and responsibilities of the position, the candidates work experience, education and training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, and external market and organizational considerations. Addtional Education Requirements Combined experience/education as substitute for minimum education Minimum Experience: 8 years Minimum Skills: Knowledge of one or more relevant programming languages (e.g., Python, C++, Goolang). Experience with Linux. Experience with Virtual LAN and/or Virtual Extensible LAN. Experience with Melanox Switches. Experience with SDN programming. Experience with Ansible, Bash and Nagios. Experience with Prometheus. Familiarity with and Simple Network Management Protocol. Experience with applicable IT protocols (e.g., Border Gateway Protocol, Secure Shell, Transport Layer Security). Experience with iptables and Network File System. Excellent written and oral communication skills. Preferred Education: Masters degree Masters degree Preferred Experience: 10 years Preferred Skills: Proven leadership ability. Experience in a university environment. Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization. If you are a current USC employee, please apply to this USC job posting in Workday by copying and pasting this link into your browser: https://wd5.myworkday.com/usc/d/inst/1$9925/9925$155714.htmld