As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be:

1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product Engineer, Quality Engineer, Validation Engineer – to identify the superset of requirements for Testability of the chip (Functional mode, Debug mode, ATPG).

2) Gain deep understanding on existing and innovative ways to insert DfT for complex analog and mixed-signal IPs, standard Macros (RAM, ROM, NVM, ADC, DAC) and complex digital logic.

3) High-quality of RTL design using Verilog and System-Verilog

4) Define Verification Plan for the implemented features and write tests, debug and get those passing at Chiptop level DV environment

5) Scan insertion, optimization, length balancing, P&R-aware rerouting of chains, Test-Point insertion, ATPG patterns generation, simulation and debug

6) Support Test Engineers during debug of patterns on new silicon, and on customer returns

7) Participate in Design & Test Review meetings and support the team for DfT
8) Generate comprehensive DfT Architecture & Design documentation and maintain it to match later updates

9) Troubleshoot and resolve issues related to DfT throughout the development lifecycle
10) Stay updated with the latest industry trends, tools, and methodologies in DfT design

Job Qualification:

• Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification.
• Minimum 3 years of experience in similar role of DfT, Digital Design & Architecture. Seeking 3-8 years total experience for this role
• Willing to relocate to Phoenix Metro area (Arizona) and minimum 3 days per week full-day presence in NXP's Chandler office
• Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills.