Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of hands-on verification experience across IP blocks, SoCs, and system-level designs.
Expertise in verification of compute and fabric datapaths.
Proficient in SystemVerilog/Verilog, UVM, and C/C++ for embedded code development.
Experience with scalable verification flows and coverage-driven strategies.
Hands-on experience with AI-driven workflows for automation in verification processes.
Ability to thrive in a startup environment with a high degree of ownership.
Responsibilities
Lead verification planning and execution from subsystem to full chip.
Collaborate with CTO and design teams to create comprehensive test plans.
Design and implement UVM testbenches with constrained-random stimulus.
Drive coverage closure using various verification techniques.
Develop and validate C/C++ firmware tests on RISC-V cores.
Extend verification through FPGA prototyping on Synopsys HAPS.
Run automated regressions and analyze bug trends for early bug detection.
Benefits
Competitive salary and benefits package
Flexible PTO
401k
Full Job Description
What you'll do
As a founding Senior ASIC Design Verification Engineer, you will own verification of the AI Persimmons inference chiplet, that runs the smallest to largest AI models. You will partner daily with the design, algorithm and compiler teams to make sure silicon matches its intended feature set and is free of critical bugs before tape-out. Your primary duties and responsibilities include:
Lead verification planning and execution from subsystem to full chip. Collaborate with the CTO, design and software teams to build test plans that validate implementation against specifications with no significant gaps.
Design and implement UVM testbenches with constrained-random stimulus, compute reference models, and scoreboards that stay portable from subsystem to chip level and are built for fast debugging.
Drive coverage closure using code, functional, and formal coverage, applying formal verification where it is most effective in the compute logic.
Develop and validate C/C++ firmware tests running on RISC-V cores to exercise compute features end to end.
Extend verification with FPGA prototyping on Synopsys HAPS, enabling software teams to run small real workloads.
Use AI agents to attack the highest-cost parts of verification: testbench generation, stimulus creation, regression triage, log analysis, and coverage closure.
Run efficient, automated regressions that conserve EDA licenses, analyze bug trends, and systematically drive bugs to closure, with a passion for finding them early.
Requirements
What You Bring To The Table:
Educational Foundation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Proven Experience: 5+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.
Compute Expertise: Verification experience on compute and fabric datapaths.
Technical Mastery: Advanced SystemVerilog/Verilog and UVM, plus C/C++ embedded code development and validation on RISC-V or similar processors.
Verification Leadership: A track record of scalable verification flows, coverage-driven strategies, assertion-based and formal verification, and data-driven calls on what to cut and what is non-negotiable before tape-out.
AI-Driven Workflows: You have built real AI-driven workflows, not just chatted with a model. You've written instructions for agents and shipped automation, ideally for regression triage, log analysis, or testbench generation.
Startup Ready: Comfortable leading and being hands-on in a small, high-ownership team, staying calm under pressure, and working on site in San Jose.
Benefits
Competitive salary and benefits package
Flexible PTO
401k
Please note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation. Direct contact of employees, officers, or board members regarding employment opportunities is strictly prohibited and will not receive a response.
