Progress toward a bachelor's, master's, or Ph.D. in electrical engineering, computer engineering, computer science, or a related field.
Coursework or project experience in loop engineering, computer architecture, digital design, VLSI, or electronic design automation.
Fluency in Python and ability to modify existing codebases.
Ability to formulate a research question and document changes and results.
Responsibilities
Study the structure of design loops and the feedback mechanisms involved.
Implement the design loop using tools like Chisel and XLS, along with simulation and physical-design tools.
Apply the loop to SoC problems, including microarchitectural exploration and RTL implementation.
Compare different loop designs based on quality, cost, reproducibility, and failure diagnosis.
Ensure the loop is reliable with clear interfaces, cached results, and regression checks.
Benefits
Gain hands-on experience in cutting-edge AI-assisted hardware/software co-design.
Work closely with a full-time researcher on a scoped research question.
Develop a rerunnable co-design loop and a comparative analysis of design strategies.
Contribute to a short report that influences team practices.
Full Job Description
Internship Duration: 6 months
Hours: 40 hours per week
Start Date: Immediately (September/October 2026)
Location: San Jose
About the role:
We are hiring a research intern in loop engineering: best practices for closed-loop flows that automate, optimize, and explore SoC designs. These are AI-assisted hardware/software co-design flows. CHIA, from UC Berkeley, is one example of a framework you may use.
You will own a scoped research question with a full-time researcher: build or extend the loop, run the experiments, and write up what the results mean for design automation.
What you will do:
Study how a design loop should be structured: which steps belong in it, what feedback each step returns, and how search, verification, and physical-design results drive the next iteration.
Implement the loop with languages and tools such as Chisel and XLS, together with simulation, software build, and physical-design tools.
Apply it to an SoC problem such as microarchitectural exploration, RTL implementation and verification, or power, performance, and area optimization.
Compare loop designs on the quality of the design point, the cost of the search, reproducibility, reuse, and how reliably a failure is diagnosed.
Make the loop reliable enough to rerun: clear interfaces between steps, cached results, regression checks, and reports that support a conclusion.
What you bring:
Progress toward a bachelor's, master's, or Ph.D. in electrical engineering, computer engineering, computer science, or a related field.
Coursework or project experience in loop engineering, computer architecture, digital design, VLSI, or electronic design automation.
Fluency in Python, and comfort reading and changing an existing codebase.
Ability to pose a small research question, keep a record of what changed, and explain the result.
Preferred:
Exposure to RTL (Verilog, SystemVerilog, Chisel, or XLS) or to an SoC design framework.
Experience with an architecture simulator or with RTL simulation.
Familiarity with an AI-assisted hardware/software co-design loop framework, such as CHIA, or with scripted hardware design, verification, or design-space exploration flows.
What success looks like:
By the end of your internship, you will have a rerunnable co-design loop applied to an SoC problem, a comparison of what worked and what it cost, and a short report on the practice the team should adopt.
