Quantum Bump Integration Engineer

GlobalFoundries Fab9 is seeking a highly skilled and motivated R&D bump process engineer to become part of our Quantum Advanced Packaging team. This role will entail driving next-generation interconnect scaling development efforts in our Advanced Packaging and Photonics Center (APPC) as well as with our partners. The primary responsibility of this position is to own development and integration of cryogenic, superconducting bumping processes enabling scalable quantum hardware packaging.

Job Summary

GlobalFoundries Fab9 is seeking a highly skilled and motivated R&D bump process engineer to become part of our Quantum Advanced Packaging team. This role will entail driving next-generation interconnect scaling development efforts in our Advanced Packaging and Photonics Center (APPC) as well as with our partners. The primary responsibility of this position is to own development and integration of cryogenic, superconducting bumping processes enabling scalable quantum hardware packaging.

Essential Responsibilities

• Lead development of cryogenic-compatible bump interconnect technologies (e.g., indium, SnAg, Cu pillar, superconducting metals).
• Define and optimize bump structures, metallurgy, and process flows for superconducting integration.
• Establish process windows to ensure electrical, thermal, and mechanical stability at mK-K temperatures (CTE mismatch, fatigue, diffusion).
• Own end-to-end bump integration flows from wafer-level processing through assembly and qualification.
• Develop and implement integration schemes across 2.5D/3D architectures (interposers, TSVs, die-to-wafer flows).
• Drive alignment between unit processes (plating, litho, CMP, bonding) and system-level packaging requirements.
• Enable rapid prototyping, ensuring smooth movement of development lots.
• Support transition from R&D to pilot/high-volume manufacturing, ensuring process robustness.
• Develop integration strategies to improve yield, reduce defectivity, and enhance manufacturability.
• Identify and analyze failure modes (e.g., delamination, interconnect resistance shifts, cryo-induced stress).
• Apply DOE, statistical analysis, and root-cause methodologies to drive continuous improvement.
• Collaborate with test teams to characterize interconnect behavior at cryogenic temperatures (DC, RF/microwave).
• Ensure bump/interconnect design supports:
  • Low-loss signal delivery
  • Minimal thermal leakage
  • Reduced crosstalk and noise (critical for qubit coherence)
• Partner with:
  • Device / qubit engineers
  • Cryogenic system teams
  • Packaging & assembly teams
  • Modeling and reliability teams
• Interface with vendors, tool suppliers, and OSAT partners for process development and scale-up.
• Drive next-generation bump scaling (pitch, height, material systems) aligned with quantum system scaling needs.
• Contribute to advanced packaging roadmap (e.g., high-density I/O, superconducting interposers).
• Scout and evaluate new materials, processes, and integration concepts.
• Work with design teams to translate system requirements into bump/interconnect specs (pitch, impedance, current limits).
• Support co-design of package + qubit + control electronics integration to reduce wiring bottlenecks and thermal load.
• Generate process documentation, specs, and integration guidelines.
• Deliver technical reports and updates to internal/external stakeholders.
• Support IP generation (invention disclosures, publications, conference contributions).

Other Responsibilities

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
• Take part in hiring of other Advanced Packaging team members.
• Mentor and guide new hires to assume their roles and responsibilities.
• Other duties as assigned by manager.

Required Qualifications

• Education - Master's in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science or related field from an accredited degree program.
• MS degree with at least 8 years of prior related work experience.
• In depth knowledge of BEOL processes and integration, bump/wafer finish integration, wafer test/probe, OSAT collaboration, and package development & assembly.
• Strong problem solving and technical trouble shooting skills including expertise in design of experiment.
• Must have at least an overall 3.0 GPA and proven good academic standing.
• Language Fluency - English (Written & Verbal).
• Travel - Up to 10%.

Preferred Qualifications

• Education - PhD education level preferred with at least 5 years of prior related work experience.
• Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
• Project management skills, i.e. the ability to innovate and execute on solutions that matter; the ability to navigate ambiguity.
• Strong written and verbal communication skills.
• Strong planning & organizational skills.

Additional Information

Expected Salary Range
$98,000.00 - $176,000.00

The exact Salary will be determined based on qualifications, experience and location.