Bachelor's degree in Electrical Engineering (Master's preferred)
8+ years of experience in SoC verification, especially for server and networking applications
Expertise in SystemVerilog/UVM with full verification lifecycle experience
Proficiency with industry-standard simulators and version control systems
Strong debugging and coverage analysis skills
Experience in developing test sequences and identifying verification gaps
Familiarity with verification of switching architectures, including packet processing.
Responsibilities
Lead functional verification of advanced ASICs, including planning and execution.
Collaborate with software and system validation teams to execute test plans on emulation platforms.
Apply directed and constrained-random verification techniques using SystemVerilog/UVM.
Debug test failures and analyze coverage results to close functional gaps.
Work with RTL designers to troubleshoot design issues.
Drive verification strategy for SoCs in server and networking applications.
Benefits
Discretionary bonus eligibility
Incentives based on performance
Comprehensive benefits package
Full Job Description
Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification-from planning and test development to debugging and coverage closure-contributing to the success of cutting-edge SoC designs.
Key Responsibilities
Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
Work with RTL designers to troubleshoot and resolve design issues.
Drive verification strategy and methodology for SoCs in server and networking applications.
Required Qualifications
Bachelor's degree in Electrical Engineering (Master's preferred).
8+ years of experience in SoC verification, particularly for server and networking applications.
Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
Proficiency with industry-standard simulators, version control, and regression systems.
Strong debugging and coverage analysis skills.
Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
Familiarity with verification of switching architectures, including packet processing and forwarding engines.
Excellent communication skills and ability to work independently with minimal supervision.
Preferred Qualifications
Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
Knowledge of Ethernet/PCIe switching and central buffer architectures.
Experience with emulation platforms and hardware-software co-verification
Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
About Astera Labs
Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
