OverviewThis full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Responsibilities- Contribute to the architecture and micro-architecture of next generation PCIe IP
- Implement these designs in System Verilog
- Collaborate with the verification team to verify the IPs
- Participate in prototyping of the IPs in cutting edge FPGAs
- Contribute to support of existing generations of the IPs
QualificationsRequired:- RTL coding: Verilog / System Verilog
- Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
- 8+ years of experience with RTL Design
- Good English skills, communication skills, and willingness to work with an international team.
Additional Desirable skills:Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
The US salary range for this full-time position is $108,300 to $201,100. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
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