Develop assertions and coverage in SystemVerilog, analyze coverage metrics, and drive coverage closure.
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
Collaborate with SoC development teams to integrate IP-level testbenches into SoC-level verification environments.
Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.
Continuously improve verification methodologies by leveraging AI/ML automation to reduce verification cycle time.
Benefits
Opportunity to work with cross-functional teams globally.
Engagement in cutting-edge verification methodologies, including AI/ML automation.
Mentorship opportunities for career growth and development.
Dynamic work environment in Chandler, Arizona.
Full Job Description
Job Description:
The dsPIC Business Unit is seeking a Principal Engineer - Verification to join our team in Chandler, Arizona. In this role, you will lead IP-level verification for dsPIC products using formal verification and UVM testbenches. You will work closely with cross-functional teams across the USA, India, and other global corporate teams to ensure high-quality verification results and timely project execution.
Key Responsibilities
Architect, develop, and maintain UVM verification environments and Formal verification environments.
Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.
Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
Collaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.
Collaborate with architects, designers, and applications teams to verify IP and product requirements and deliver quality results on schedule.
Provide technical support and mentoring to verification engineers and drive projects to completion on schedule.
Continuously improve verification methodologies by leveraging AI/ML automation to reduce the cycle time of verification.
Requirements/Qualifications:
Required Qualifications
Bachelor's or master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Minimum 10+ years of experience in functional verification.
Strong expertise in SystemVerilog language, assertions, and UVM methodology.
Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.
Excellent understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
Strong communication, teamwork, and problem-solving skills.
Highly motivated, detail-oriented, and committed to delivering quality results on time.
Preferred Qualifications
Demonstrated success in mentoring engineers and leading verification efforts across global teams.
Experience driving methodology improvements and automation initiatives.
Travel Time:
0% - 25%
Physical Attributes:
Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:
sitting 90%
About Microchip Technology
Microchip Technology is an American semiconductor company headquartered in Chandler, Arizona. The company was founded in 1989 and has been providing microcontroller and analog semiconductors for over 30 years. Microchip Technology operates in over 100 locations in 70 countries and has more than 18,000 employees worldwide. The company's products include microcontrollers, memory, and other analog and mixed-signal products. Microchip Technology's mission is to provide innovative solutions for a wide range of applications, including automotive, industrial, and consumer electronics.
