RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE REQUIRED FOR START: Yes

CLEARANCE TYPE: Top Secret

TRAVEL: NoDescription

We are seeking an Engineer / Principal Research and Advanced Design Hardware Engineer to support a research area associated with our key lab environment within the Battlespace Architecture Systems and Technology (BAST) organization. The program technologies include 5G/NextG communications, machine learning, cybersecurity, cloud computing, and future wireless technologies in support of tactical applications for the warfighter. The position is located in El Segundo, CA, Telecommute/remote is not an option for this position. This position's standard work schedule is 9/80, to allow employees every other Friday off.

Responsibilities will include working through all phases of the Hardware development cycle including design, development, integration, and test. The selected individual will conduct peer reviews of Hardware-related products, hardware designs, and additional technical documents. Successful candidates are expected to be able to understand system requirements and how they apply to system design. Individuals must be self-starters and able to efficiently operate in a team environment. Existing engineering and system specialists will be made available to assist with any activities associated with executing primary tasking. However, the selected individual will be expected to prioritize and make recommendations to Technical Leads, as required, to implement tasking assigned.

Job Responsibilities include, but are not limited to, the following:
• Work in a fast-paced environment with high expectations, significantly diverse assignments, and collaborative team settings across all levels
• Participate in the full hardware development life cycle including requirements, design, implementation, qualification, and delivery of hardware products to our customers
• Define subsystem functional decomposition into CPUs, GPUs, FPGAs, and software
• Define processor capabilities such as Gbps, latencies, throughputs
• Define subsystem interface requirements, voltage levels, and suitable cabling
• Perform integration activities including laboratory setup, cabling and integration with oscilloscopes, logic analyzers, spectrum analyzers, synthesizers
• Collaborate with multidisciplinary teams - including Systems Engineering, Digital Engineering, Software, and Integration & Test
• Interpret and apply system requirements to system design and implementation, ensuring defined completion criteria are met

Basic Qualifications:
• Engineer: Bachelor's degree in electrical engineering, Computer Engineering, or related STEM discipline and 2 years of relevant experience; or Master's degree with 0 years of experience
• Principal: Bachelor's degree in electrical engineering, Computer Engineering, or related STEM discipline and 5 years of relevant experience; or Master's degree with 3 years of experience
• Experience with subsystem functional decomposition into hardware components (e.g., CPUs, GPUs, FPGAs) and software components
• Experience with hardware component and subsystem performance concepts such as Gbps, latencies, and throughput, and ability to support definition of related requirements
• Experience defining, implementing, and testing hardware interfaces (e.g. voltage levels, signaling standards, and selection of suitable cabling/connectors) suitable for use on Department of War (DOW) platforms
• Experience integrating and testing in a laboratory environment: bench/rack setup, cabling, and use of test equipment such as oscilloscopes, logic analyzers, spectrum analyzers, and signal generators/synthesizers
• Strong written and verbal communication skills and ability to work effectively on a multi-disciplinary team
• Active DoD Secret clearance (background investigation completed within the last 6 years)
• Ability to obtain and maintain DoD Top Secret Clearance and must be obtained within a reasonable amount of time as determined by the company to meet its business needs
• Ability to obtain and maintain initial Special Program Access (SAP/PAR). This SAP/PAR must be obtained within a reasonable amount of time as determined by the company to meet its business needs

Preferred Qualifications:
• Familiarity with standard digital and/or mixed-signal interfaces (e.g., LVDS, Ethernet, PCIe, serial links, or similar)
• Familiarity with FPGA development
• Familiarity with developing and maintaining indentured parts lists and/or bill of materials at the subsystem and system level
• Experience with Communication Protocols (I2C, SPI, UART, PCIe, Ethernet, UDP, TCP)
• Hands-on hardware integration and testing experience
• Ability to debug complex integrated applications or test setup issues
• Active DoD Top Secret (TS) security clearance

Primary Level Salary Range: $91,800.00 - $137,600.00

Secondary Level Salary Range: $114,000.00 - $171,000.00

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.