Lattice Semiconductor

Principal Engineer - CAD Design Engineering & EDA Infrastructure

Enterprise Technology
11 - 15 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree in electrical or computer engineering or a related field
  • 15+ years in semiconductor design, with a minimum of 7 years in EDA methodology leadership
  • Strong expertise in RTL design, verification, synthesis, and timing analysis
  • Background in compute infrastructure and cloud-based design environments
  • Proven experience in leading global teams and vendor negotiations
  • Excellent communication and strategic planning skills

Responsibilities

  • Define long-term vision for EDA methodologies and infrastructure
  • Architect and implement design flows for various design stages
  • Manage compute farms, license servers, and tool deployments
  • Develop and implement a GenAI strategy for methodologies
  • Collaborate across teams to align methodologies with project needs
  • Evaluate and benchmark EDA tools from major vendors
  • Lead innovation in automation and AI/ML-driven design processes
  • Build and mentor a high-performing CAD/EDA engineering team
  • Establish best practices and training programs for design teams
  • Identify and mitigate risks in tool flows and project schedules

Benefits

  • Comprehensive healthcare and retirement plans
  • Paid time off and holidays
  • Variable incentive compensation and/or equity opportunities
  • Potential for professional development and training
  • Flexible work environment options
Full Job Description
Job Description:

Principal Engineer - CAD Design Engineering & EDA Infrastructure

We are seeking an experienced and highly technical Principal Engineer to lead the strategy, architecture, development, and operational excellence of our CAD and EDA Infrastructure. This role is responsible for enabling world-class semiconductor and hardware design teams through scalable design environments, automation, tool optimization, cloud adoption, and engineering productivity initiatives.

The ideal candidate combines deep expertise in semiconductor design flows, EDA tools, infrastructure engineering, and large-scale automation with strong leadership and cross-functional collaboration skills.

Key Responsibilities

CAD & EDA Infrastructure Leadership
  • Define and execute the vision, roadmap, and strategy for CAD and EDA infrastructure supporting ASIC, SoC, IP, and verification teams.
  • Lead the design, deployment, and maintenance of highly scalable and secure engineering environments.
  • Drive infrastructure modernization initiatives including cloud-enabled design workflows, hybrid compute environments, and next-generation engineering platforms.
  • Partner with design, verification, implementation, and architecture teams to understand evolving tool and infrastructure requirements.

EDA Tools & Design Flow Development
  • Optimize RTL-to-GDSII design flows across synthesis, place-and-route, STA, DFT, verification, emulation, and signoff.
  • Evaluate, deploy, and support industry-standard EDA tools from Synopsys, Cadence, Siemens/Mentor, and other vendors.
  • Standardize methodologies and best practices across global engineering teams.
  • Improve tool reliability, performance, and user productivity through automation and workflow optimization.


Automation & Engineering Productivity
  • Drive automation using Python, Tcl, Perl, Shell scripting, and modern software engineering practices.
  • Build self-service platforms and dashboards for monitoring tool usage, licenses, compute resources, and design flow metrics.
  • Reduce design cycle times through process optimization and infrastructure innovation.
  • Implement CI/CD and DevOps practices for CAD environments and engineering workflows.


Infrastructure & Compute Management
  • Architect and manage large-scale Linux-based compute farms and distributed job scheduling systems.
  • Optimize storage, networking, HPC clusters, and cloud resources to support demanding EDA workloads.
  • Manage EDA license infrastructure, capacity planning, and utilization optimization.
  • Ensure high availability, reliability, security, and compliance of engineering environments.


Technical Leadership
  • Serve as a subject matter expert and trusted advisor to design leadership and engineering teams.
  • Mentor engineers and contribute to the growth of CAD and infrastructure talent.
  • Influence technology decisions and provide guidance on future engineering platform investments.
  • Lead root-cause analysis and resolution of complex technical issues impacting engineering productivity.


Required Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
  • 12+ years of experience in semiconductor design methodologies, CAD engineering, or EDA infrastructure.
  • Deep understanding of ASIC/SoC design and verification flows.
  • Strong expertise with Linux/Unix environments and distributed computing systems.
  • Hands-on experience with leading EDA platforms from Synopsys, Cadence EDA.
  • Advanced programming and automation skills in Python, Tcl, Shell, or similar languages.
  • Experience managing large-scale compute farms, license servers, storage systems, and enterprise infrastructure.
  • Strong analytical, problem-solving, and stakeholder management skills.


Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range
230732.01

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

About Lattice Semiconductor

Lattice Semiconductor Corporation is an American manufacturer of high-performance programmable logic devices (FPGAs, CPLDs, & SPLDs). Founded in 1983, the company is headquartered in Portland, Oregon, and employs about 1,250 people. Lattice Semiconductor went public in 1989 and is traded on the NASDAQ stock exchange under the symbol LSCC. The company's products are used in communications, computing, industrial, automotive, and consumer markets.
Learn more about Lattice Semiconductor
Size
856 employees
Market Cap
$8.7 billion
Industry
Net Income
$47.3 million
Founded
1983
5 Year Trend
+3.8%
Revenue
$408.1 million
NASDAQ

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