Application close date:
Applications will be accepted on an ongoing basis until the requisition is closed.
Job DescriptionThe Emerging Systems business unit at Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of 5,408 optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide
The digital system comprises two ASICs: a high-throughput modem and a DSP-intensive digital beamforming (DBF) chip, with first tapeout targeted for 2027. This is Blue Origin's first in-house silicon, which means the development strategy, methodology, and infrastructure are being defined now - and we are hiring senior engineers and technical leads to define them.
Our strategy treats constrained-random simulation, formal methods, and pre-silicon hardware platforms as equal first-class tools, with dedicated engineers for each. This role owns the hardware platforms end to end, across two complementary capabilities:
- Emulation primary targeting pre-silicon vehicle for design and verification bring-up,
- FPGA prototyping driving DSP and beamforming datapaths against real data converters, RF front ends, antenna hardware, and lab instrumentation at scaled sample rates.
You will define the platform strategy, select and deploy the hardware, build the flows, and stand up a nightly image service that the rest of the program runs on - because none of it exists today.
Wireless communications experience is welcome but not required. If you want to define methodology and tooling rather than consume someone else's, that opportunity is genuinely available here.
Responsibilities:- Define and build Blue Origin's pre-silicon emulation and prototyping capability from the ground up.
- Develop platform strategy, flows, and infrastructure, and lead tradeoff studies covering capacity, build turnaround, debug visibility, and cost.
- Evaluate and recommend platform choices, including commercial emulation systems (e.g., Palladium, Veloce, ZeBu), commercial prototyping systems (e.g., Protium, HAPS), off-the-shelf boards, and custom board solutions.
- Own the end-to-end build flow: partitioning, synthesis, constraints, implementation, and timing closure for large SoC and subsystem designs across single- and multi-FPGA targets.
- Adapt designs for the platform, including clock and reset restructuring, memory model substitution, and replacement of hard IP with platform equivalents.
- Define the rate-reduction strategy for DSP and beamforming prototyping - decimation, clock ratios, reduced beam and element counts - and establish, with architecture and modeling, the fidelity criteria that show a scaled slice is representative of the full design.
- Build hardware-in-the-loop platforms connecting DSP and beamforming datapaths to real converters, RF front ends, and antenna hardware, including data converter interfacing, coherent multi-channel clock distribution, and latency-deterministic data paths.
- Establish and operate a nightly build service producing qualified images on a predictable cadence, with versioning, release notes, and rollback, and define the qualification tests that validate each image before release.
- Develop transactors, speed bridges, host-side software, and test harnesses that connect designs to reference models, test equipment, and real-world interfaces.
- Manage platform capacity, scheduling, and allocation across competing users, and forecast future capacity needs against program milestones.
- Debug at platform level - signal capture, waveform tracing, transaction-level debug - and triage failures with design and verification teams to isolate root cause.
- Partner with RF, antenna, and DSP teams on lab integration, calibration, and end-to-end signal chain validation.
- Produce and maintain user documentation, onboarding material, and usage guidance so teams can operate independently.
Basic Qualifications:- BS+10, MS+8, or PhD+6 years in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
- Hands-on experience with FPGA implementation tools and flows (synthesis, constraints, place and route, timing closure) and with commercial emulation platforms.
- Strong hands-on RTL skills in SystemVerilog or Verilog, including the ability to read, modify, and debug production RTL you did not author.
- Experience defining and deploying FPGA prototyping or emulation flows, including build automation and release management.
- Experience bringing up large digital designs on FPGA or emulation platforms.
- Proficiency in Tcl, Python, or similar scripting for build automation, flow development, and CI integration.
- Experience with lab and board-level bring-up and debug, using on-chip probes, waveform capture, and lab instrumentation.
- Experience supporting internal users of a shared platform or flow, including triage, documentation, and direct technical support.
- Ability to work effectively across cross-site, multidisciplinary engineering teams.
Preferred Qualifications:- Background in space-based communications, wireless communications, or modem/baseband hardware.
- Experience prototyping DSP or communications datapaths, including LDPC/FEC, framing, or beamforming logic.
- Experience with high-speed interfaces on FPGA - JESD204B/C, multi-gigabit transceivers, DDR memory controllers, PCIe, or Ethernet.
- Experience with mixed-signal or RF lab integration, including data converter interfacing, coherent clocking and jitter budgets, and instrumentation-driven test.
- Experience with host-side software development (C/C++, DPI, SCE-MI) for transactors, speed bridges, and test harnesses.
- Experience bringing up embedded processors and boot flows on FPGA, including ARM-based SoC FPGAs or soft-core processors.
- Familiarity with advanced verification methodology, sufficient to reuse and adapt simulation content on platform.
- Experience applying AI/ML or LLM-based tooling to build triage, log analysis, or flow automation.
Base Pay Range for:
CA applicants is $230,398.00 - $322,556.85
Other site ranges may differBenefits- Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
- Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.
