Bachelor's in Electrical Engineering required; Master's preferred.
8+ years of experience in verifying complex SoCs for Server, Storage, and Networking applications.
Familiarity with industry-standard simulators and revision control systems.
Ability to manage multiple tasks with minimal supervision.
Entrepreneurial mindset with a customer-focused approach.
Authorized to work in the US and available to start immediately.
Responsibilities
Lead the full verification lifecycle from planning to debugging and coverage closure.
Develop and execute test plans in collaboration with software and system validation teams.
Utilize System Verilog/UVM/C/C++ for verification processes.
Employ hybrid verification techniques, including directed and constrained random methods.
Identify and implement coverage measures to ensure high-quality tape-out.
Work independently to create test sequences and stimuli for RTL debugging.
Benefits
Collaborative work environment with cross-functional teams.
Opportunities for professional growth and development.
Access to advanced verification tools and technologies.
Flexible work arrangements to support work-life balance.
Full Job Description
Job Overview We are looking for a Principal Design Verification Engineer with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Basic qualifications
Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred.
≥8 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications.
Knowledge of industry-standard simulators, revision control systems, and regression systems.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in the US and start immediately.
Required Experience
Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.
Preferred Experience
Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
Experience with directed test based methodologies, cache verification and formal methods.
The base salary range is USD 185,000.00 - USD 240,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
About Astera Labs
Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
