Bachelor's degree in electrical engineering or related field with 5+ years of ASIC physical design experience, or a master's degree with 3+ years of experience.
Proficiency with Synopsys ICC2, Fusion Compiler, or Cadence Innovus, with real tapeout experience.
Strong scripting skills in TCL, Python, or Perl for automation and problem-solving.
Solid understanding of advanced-node design challenges at 7nm and below, including FinFET effects and multi-patterning.
Experience with logical and physical synthesis flows; familiarity with AI-driven optimization methodologies is a plus.
Excellent communication skills for conveying complex concepts to diverse audiences.
Willingness to travel to customer sites on short notice for critical support.
Responsibilities
Support customer engagements on advanced-node designs using Synopsys tools to meet PPA targets.
Develop and enhance physical design methodologies and automation solutions to improve design quality.
Debug complex physical design challenges including timing closure and power optimization.
Build tailored methodology recommendations based on customer-specific constraints and technologies.
Contribute to AI-assisted design optimization initiatives using data-driven approaches.
Collaborate with R&D and product management to translate customer needs into product enhancements.
Travel to customer sites for onsite support, training, and design reviews under tight deadlines.
Benefits
Comprehensive health and wellness benefits.
Financial benefits including potential bonuses and equity.
Supportive work environment with a focus on employee well-being.
Opportunities for professional development and growth.
Full Job Description
Descriptions & Requirements
Job Description and Requirements
What You'll Be Doing
Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler, helping them hit PPA targets under real schedule and resource constraints
Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow
Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints
Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific context
Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve implementation challenges that traditional methods struggle with
Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next release
Travel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high-stakes tape-out pressure
The Impact You Will Have
Enable customers to achieve timing closure and tape-out success on advanced-node designs that define next-generation AI, mobile, and datacenter products
Build automation and methodology improvements that get reused across multiple customer engagements, multiplying your impact across dozens of designs
Shape the roadmap of Synopsys physical design tools by feeding real customer challenges directly into R&D, influencing features that thousands of engineers will use
Reduce design cycle time and improve PPA outcomes for customers working at the cutting edge of semiconductor technology, where every percentage point of performance or power matters
Mentor field teams and customers on advanced physical design techniques, raising the bar for how complex designs get implemented across the industry
Help drive adoption of AI-driven optimization methodologies that change how physical design gets done, not just incrementally but fundamentally
Strengthen customer relationships by being the engineer they call when a design is stuck and they need someone who can actually solve the problem, not just escalate it
What You'll Need
Bachelor's degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master's degree with 3+ years of experience
Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, you have used these tools on real tapeouts, not just in training
Strong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems that do not have a button in the GUI
Solid understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, electromigration, and the tradeoffs that come with each
Experience with logical and physical synthesis flows, and familiarity with AI-driven optimization methodologies is a strong plus
Excellent communication and presentation skills, you can explain a complex timing closure strategy to a customer engineering team and a high-level roadblock to their management in the same meeting
Willingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phases
Who You Are
You can walk into a customer meeting with incomplete information, ask the right questions, and leave with a clear plan that the team actually believes in
When a design is failing timing by 500ps and the customer is two weeks from tape-out, you do not panic, you methodically work the problem until you find the path to closure
You write scripts that other engineers can actually read and modify, not just code that works but code that scales across a team
You push back when a methodology recommendation does not fit the customer's reality, even if it means more work to find the right answer
You can explain a complex physical design tradeoff to a VP in two sentences without losing the nuance, and then turn around and debug a TCL flow issue with an engineer
You treat customer problems like your own, not because you have to but because you care about the outcome and you know your work directly affects whether their chip succeeds or fails
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process. Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
About Synopsys Inc
Synopsys, Inc. is an American electronic design automation company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, hardware description language (SystemC, SystemVerilog/Verilog, VHDL) simulators, as well as transistor-level circuit simulation. The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems.
