BS w/ 4+ years, MS w/ 2+ years, or PhD with minimal experience in physical design
Proven track record in complex silicon tapeouts
Hands-on involvement in block physical implementation
Strong coding skills in Python, Bazel, and TCL
Experience developing physical design tools and methodologies
Solid understanding of microarchitecture and timing closure
Familiarity with industry-standard physical design tools and flows
Responsibilities
Develop and maintain tools and methodologies for physical design
Oversee floorplan block implementation from planning to signoff
Collaborate with RTL teams to optimize implementation solutions
Analyze and enhance designs for timing, power, and area
Work with EDA vendors and ASIC partners to achieve design objectives
Benefits
Opportunity to work on cutting-edge AI technology
Collaborative and innovative team environment
Focus on safety and responsible AI deployment
Inclusive workplace that values diverse perspectives
Development of skills in advanced physical design techniques
Full Job Description
About the Role We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.
You'll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon's performance and cost efficiency, as well as the team's execution velocity and quality.
In this role, you will:
Develop, build and own tools, flows and methodologies for physical implementation
Own physical implementation of floorplan blocks from floorplanning to final signoff
Collaborate with RTL designers to drive optimal block implementation solutions
Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners
Qualifications:
BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
Demonstrated success in taping out complex silicon designs
Hands-on experience with block physical implementation and PPA convergence
Strong coding experience with python, bazel, TCL
Strong experience building physical design tools, flows and methodologies
Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation
Bonus:
Experience with AI or HPC-focused chips
Experience with optimizing PPA for high performance compute cores
Hands-on experience with top-level design methodologies
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
About OpenAI
OpenAI is an artificial intelligence research laboratory consisting of the for-profit corporation OpenAI LP and its parent company, the non-profit OpenAI Inc. The company was founded in 2015 by a group of technology leaders, including Elon Musk, Sam Altman, Greg Brockman, Ilya Sutskever, and John Schulman. OpenAI's mission is to develop and promote friendly AI for the betterment of humanity. The company has developed a number of cutting-edge AI technologies, including GPT-3, a language processing system that can generate human-like text. OpenAI has received funding from a number of high-profile investors, including LinkedIn co-founder Reid Hoffman and venture capitalist Peter Thiel.
