Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
7+ years of hands-on experience in physical design and implementation.
Proficiency in EDA tools like Genus, Innovus, Tempus, and Quantus.
Deep understanding of physical design flows and methodologies.
Expertise in sub-7nm node technologies is preferred.
Responsibilities
Execute synthesis, PNR, and STA for ASIC chip partitions within strict schedules.
Collaborate with architects, RTL designers, and DFT engineers to resolve implementation issues.
Close EM/IR and drive LEC and physical verification signoff for assigned partitions.
Identify and address potential physical design challenges with the design team.
Refine implementation and physical design methodologies, including EMIR and PDN.
Troubleshoot flow issues and work with EDA vendors for resolutions.
Benefits
Onsite work location in San Jose, CA.
C2C engagements allowed.
Opportunity to work with cutting-edge technologies in ASIC design.
Full Job Description
Job Title : Physical Design Engineer
Client: Arrow Electronics
Experience Required: 5+ years (Relevant)
Work Location: San Jose ,CA, onsite
Visa: All visa, except H1B transfer
C2C engagements are allowed.
Job Responsibilities:
Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Genus ,Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
Genus ,Innovus are must have
Preferred Qualifications:
7+ years of experience in physical design roles and related activities.
Proven ability to adhere to tight schedules and implement low-power design techniques.
Experience in System-on-Chip (SoC) design and implementation.
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.
