Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Locations (San Diego, Santa Clara, Austin TX) Compensation:The expected annual base salary range for this position is
$123,100.00 to $250,000.00. Actual compensation will be determined based on factors such as experience, education, skills, qualifications, location, and business needs.
We are seeking highly motivated Physical Design Engineers across multiple career levels to join our growing ASIC implementation team. In this role, you will contribute to the development and execution of advanced physical design methodologies for complex, high-performance, low-power SoCs and IP blocks. You will work closely with architecture, RTL, DFT, verification, CAD, and product engineering teams to implement and deliver industry-leading designs from synthesis through final tapeout.
The ideal candidate possesses strong technical expertise in physical implementation, timing closure, low-power design techniques, automation, and design optimization. Depending on experience and demonstrated technical leadership, candidates may be considered for Engineer, Senior Engineer, Staff Engineer, or Principal Engineer opportunities. Physical Design responsibilities include floorplanning, power planning, place and route, clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff activities. The role supports Qualcomm's advanced SoC and core design programs across GPU, Multimedia, AI, Compute, Connectivity, Modem, DDR, Audio, and other next-generation technologies.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Responsibilities by LevelEngineerExperience: 2+ years industry experience
- Support implementation and physical design closure of ASIC and SoC blocks.
- Execute floorplanning, placement, CTS, routing, timing analysis, and physical verification tasks under technical guidance.
- Assist in identifying and resolving timing, congestion, power, and physical implementation challenges.
- Develop scripts and automation solutions to improve design productivity.
- Collaborate with cross-functional teams to support successful project execution.
Senior EngineerExperience: 4+ years industry experience
- Independently own physical implementation and signoff for complex design blocks.
- Drive timing closure, power optimization, signal integrity analysis, and design convergence across multiple operating modes and corners.
- Develop and improve implementation methodologies and automation flows.
- Analyze and resolve complex physical design issues impacting schedule, quality, or performance targets.
- Mentor junior engineers and contribute to technical best practices.
Staff EngineerExperience: 8+ years industry experience
- Lead physical design execution for large subsystems or critical SoC partitions.
- Define implementation strategies to achieve aggressive power, performance, area, and schedule objectives.
- Drive cross-functional technical alignment among Design, DFT, CAD, Verification, and Product Engineering teams.
- Develop scalable methodologies, flow improvements, and automation solutions adopted across projects.
- Act as a technical subject matter expert in advanced physical implementation and design closure.
Senior Staff EngineerExperience: 12+ years industry experience- Lead implementation and signoff of highly complex subsystems and full-chip partitions.
- Drive technical decisions impacting multiple products, programs, or business-critical deliverables.
- Develop and institutionalize scalable methodologies, flows, and automation frameworks used across engineering teams.
- Provide technical leadership across multiple project teams and mentor Staff and Senior Engineers.
- Partner with architecture, design, and CAD teams to solve complex power, performance, area, and scalability challenges.
- Influence implementation strategy, design planning, technology adoption, and execution across multiple tapeouts.
- Recognized as a subject matter expert in physical design and design closure.
Principal EngineerExperience: 15+ years industry experience
- Provide strategic technical leadership across multiple SoC programs and technology initiatives.
- Define and influence organizational physical design methodologies, implementation roadmaps, and best practices.
- Lead chip-level implementation, signoff, and design closure activities for highly complex products.
- Drive technology adoption, methodology innovation, and engineering excellence across teams.
- Mentor senior technical talent and serve as a recognized expert within Qualcomm's ASIC organization.
- Influence architecture, implementation strategy, and long-term execution plans across product portfolios.
Minimum Qualifications- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and relevant experience in ASIC design, implementation, verification, validation, integration, or related engineering disciplines.
- Experience with digital ASIC physical implementation methodologies.
- Understanding of power, performance, area, timing, and physical design tradeoffs.
- Experience working in Linux/Unix environments.
- Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages.
- Strong analytical, problem-solving, and debugging skills.
Preferred Qualifications- Experience with complete Physical Design Flow from synthesis through tapeout.
- Physical design expertise including floorplanning, power planning, placement, CTS, routing, timing optimization, and closure
- Experience using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static Timing Analysis and timing closure experience using Synopsys PrimeTime.
- Knowledge of MMMC implementation methodologies and advanced-node design closure.
- Experience with DFT-aware implementation and functional timing constraints.
- Experience with RC extraction, signal integrity analysis, cross-talk analysis, ECO implementation, and formal verification.
- Experience with low-power implementation techniques, UPF methodologies, and power domain analysis.
- Strong communication, collaboration, and technical leadership capabilities.
Technical Expertise AreasSuccessful candidates may possess expertise in one or more of the following areas:
- Physical Design & Implementation
- ASIC Place & Route
- Floorplanning
- Power Planning
- Clock Tree Synthesis (CTS)
- Static Timing Analysis (STA)
- MMMC Timing Closure
- Signal Integrity Analysis
- EM/IR Analysis
- Physical Verification
- DFT Implementation
- Low Power Design Methodologies
- Design Automation & Scripting
- SoC Integration
- Advanced Process Nodes
- Methodology Development
CompensationThe expected annual base salary range for this position is
$123,100.00 to $250,000.00. Actual compensation will be determined based on factors such as experience, education, skills, qualifications, location, and business needs.
In addition to base salary, Qualcomm offers a comprehensive benefits package designed to support employees and their families, including opportunities for annual incentive compensation, stock awards, health and wellness programs, retirement benefits, paid time off, and professional development opportunities.
Because this posting supports multiple career levels, compensation will vary depending on the candidate's final level and qualifications.
Pay range and Other Compensation & Benefits: ₹0.00 - ₹0.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
