Company:Qualcomm Technologies, Inc.
Job Area:Engineering Group, Engineering Group > ASICS Engineering
What you will be doing :
- Micro-architect, design and validate RTL for blocks and modules of SOC Interconnects, Interconnect Caches and memory subsystems, and power and system level design
- Identify advanced ways to optimize hardware design for better performance, power, and cost
- Evaluate the hardware feasibilities of complex algorithms and requirements
- Develop micro architecture and specification of the new generation design
- Develop RTL for the corresponding micro architecture
- Provide essential verification and debugging activities for the corresponding design throughout the entire project cycles
- Optimize the silicon cost and improve clock speed
- Troubleshoot silicon issues with products relevant to the corresponding design
Key-qualifications:- The team is looking for candidates with 3+ years of experience.
- Experience or course work in Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, coverage-based design verification
- Experience or course work in Computer Architecture, Computer Arithmetic, Low power design, C/C++/Python programming languages is desired.
- Experience or course work in designing RTL for CPU, cache controller blocks in ASIC is a plus!
- Good communication skill and desire to work as a team player
Qualifications:* Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5 OR
* Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with a GPA > 3.5 OR
* PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field
- Prior experience in ASIC Design and DV is a plus.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
