New College Grad - HBM Design Architect

Micron's High Bandwidth Memory (HBM) Design Architecture team develops memory solutions for AI accelerators, high-performance computing, and data centers. Within this team, our Roadmap and Pathfinding group identifies, assesses, and enables new memory and advanced packaging technologies for future HBM products, translating them into credible product architectures. As an HBM Design Architect, you will perform first-principles architecture analysis for current and future HBM/DRAM products - spanning dynamic power, PDN, thermal, timing, and area trade-offs - and run the circuit and CAD simulations needed to back them up. You will work closely with designers and technologists to develop architectural solutions, and your work will directly inform which architecture and technology options move forward toward product. Responsibilities • Perform architecture-level analysis for HBM/DRAM products, including dynamic and static power, PDN/IR drop, thermal behavior, timing, and area trade-offs • Build first-principles models and contributor breakdowns (array, periphery, datapath, I/O, TSV) and correlate them with simulation and silicon data • Set up and run circuit simulations (SPICE/HSPICE, FineSim, PrimeSim, Spectre, or equivalent) and associated CAD flows - schematic setup, parasitic extraction, and post-layout simulation - to validate architectural assumptions • Assess the impact of new technologies on product metrics, including advanced DRAM nodes, 3D stacking, scaled-pitch hybrid bonding, and BEOL/TSV changes • Partner with circuit designers, process technologists, and packaging engineers to develop and quantify architectural solutions • Develop scripts, calculators, and automation (Python or equivalent), leveraging AI-assisted workflows (LLMs, Code Assist, agentic AI tools) to accelerate modeling, simulation setup, and data analysis • Communicate results clearly in architecture reviews and cross-functional working groups Minimum Qualifications • BSEE or related field with 0-2 years of relevant experience, or MS/PhD with 0-2+ years • Solid foundation in CMOS circuit design and device physics • Working knowledge of DRAM fundamentals (cell/array operation, sensing, basic timing) • Understanding of power delivery and power analysis (CV²f, leakage, IR drop) and thermal concepts for semiconductor dies • Hands-on experience with circuit simulation (SPICE/HSPICE, FineSim, or equivalent) and Cadence Virtuoso or similar CAD environments • Proficiency in Python, Tcl, Perl, or another scripting language Preferred Qualifications • Coursework, research, or experience in DRAM/HBM design, TSV-based 3D integration, or advanced packaging • Exposure to PDN/power analysis tools or thermal simulation (compact thermal models, FEA/CFD) • Familiarity with semiconductor process technology (FEOL/BEOL, interconnect materials, bonding) • Experience using AI-enabled tools (LLMs, AI assistants, Code Assist/Roo Code, or agentic AI solutions) for engineering automation and analysis • Strong analytical skills with a curiosity-driven, first-principles approach • Ability to communicate technical trade-offs clearly to designers and technologists