Lead Technical Program Manager

Job Details:

Job Description:

About the Role

Altera is seeking a Lead Technical Program Manager to provide strategic technical program leadership for the development and delivery of next-generation FPGA products. This is a high-impact, cross-functional leadership role responsible for driving execution across complex, multi-disciplinary engineering programs spanning silicon, architecture, IP, hardware, software, firmware, validation, and manufacturing readiness.

The Lead Technical Program Manager will operate across organizational boundaries to establish program strategy, drive execution against critical business and engineering objectives, and ensure alignment across highly technical teams. This individual will partner closely with senior engineering leaders, product management, and executive stakeholders to translate complex technical challenges into actionable execution plans and deliver products from early definition through production.

The ideal candidate brings deep silicon/hardware design background (ordeep FPGA and semiconductor domain expertise), exceptional technical program leadership capabilities, and a proven ability to lead complex programs where success requires influence across multiple organizations rather than direct authority.

Responsibilities

• Provide strategic technical program leadership for complex, high-visibility FPGA product development programs spanning architecture, silicon, IP, hardware, software, firmware, validation, and production.
• Own program strategy, execution frameworks, critical milestones, and cross-functional alignment from early product definition through silicon bring-up, validation, sampling, and production release.
• Partner with senior engineering and product leaders to translate product and business objectives into integrated technical roadmaps, execution plans, schedules, and measurable milestones.
• Drive alignment across multiple engineering organizations and geographically distributed teams, establishing clear ownership, accountability, dependencies, and decision-making mechanisms.
• Lead cross-functional resolution of complex technical and organizational challenges, including integration issues, schedule constraints, resource conflicts, technical trade-offs, and critical-path risks.
• Establish and manage program-level risk frameworks, proactively identifying issues that could impact product quality, schedule, cost, or business objectives and driving mitigation strategies.
• Coordinate execution across RTL, design verification, architecture, physical design, firmware, software, system engineering, validation, and operations teams.
• Drive technical readiness and execution across pre-silicon and post-silicon phases, including design completion, verification, tape-out, silicon bring-up, validation, debug, customer readiness, and production ramp.
• Develop executive-level program reporting that provides clear visibility into schedule, technical health, risks, dependencies, resource requirements, and key decisions.
• Facilitate senior leadership reviews and drive timely decision-making on issues requiring organizational alignment or executive escalation.
• Establish and continuously improve program management methodologies, operating mechanisms, tools, and reporting frameworks that increase predictability and execution discipline across engineering.
• Identify opportunities to improve development processes, cross-functional collaboration, and organizational execution across the broader product development lifecycle.
• Mentor and provide guidance to other Technical Program Managers and program leaders, helping establish consistent best practices across the organization.
• Represent program execution and technical program management in senior leadership forums and cross-functional planning activities.

Leadership Profile

The successful candidate will operate as a strategic technical leader and program execution partner to Altera's engineering organization. This role requires someone who can move comfortably between high-level product strategy and detailed technical execution, understand the engineering challenges well enough to challenge assumptions and facilitate decisions, and create alignment across organizations that may have competing priorities.

The Lead Technical Program Manager will be expected to lead through influence, establish clarity in ambiguous situations, anticipate execution challenges before they become critical, and create the operating mechanisms necessary to deliver complex FPGA products predictably and successfully.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$187,000 - $270,700 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Software Engineering, or a related technical discipline, with 12+ years of experience in Technical Program Management, Engineering Program Management, or technical engineering leadership roles.
• 8+ years of experience leading complex, cross-functional semiconductor, FPGA, ASIC, silicon, or hardware/software development programs involving multiple engineering organizations.
• Strong silicon/hardware design domain expertise with a deep understanding of HW/FW/SW interactions, enabling effective engagement across architecture, RTL, design verification, physical design, firmware, software, system, and validation teams.
• Proven leadership across the full Product Lifecycle (PLC), from product definition and architecture through development, verification, tape-out, silicon bring-up, validation, debug, sampling, and production.
• Demonstrated ability to translate complex technical challenges into structured execution strategies, establish program priorities, manage critical paths and dependencies, and drive organizations toward measurable outcomes.
• 7+ years of experience leading programs across multiple organizations and geographically distributed international teams, with a demonstrated ability to influence senior stakeholders and drive accountability without direct authority.
• Proven experience identifying and managing technical, schedule, resource, integration, and execution risks, including the ability to evaluate trade-offs and drive mitigation strategies.
• Demonstrated ability to communicate complex technical and program issues effectively to senior engineering leaders, executives, and cross-functional stakeholders.

Preferred Qualifications

• 5+ years of technical experience in one or more of the following areas: Transceivers, Embedded Systems (particularly ARM), Config and Security, PCIe, Ethernet, or ASIC Design / Design Verification (DV).
• Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of experience working directly with FPGA, ASIC, semiconductor, or silicon-based product development.
• Deep experience with pre- and post-silicon execution, including verification, validation, silicon bring-up, debug, characterization, and production readiness.
• Experience leading programs involving next-generation or highly complex semiconductor products with significant technical dependencies and cross-organizational execution challenges.
• Experience establishing program governance, operating mechanisms, and execution frameworks across large engineering organizations.
• Experience working directly with executive leadership to communicate program health, strategic risks, technical trade-offs, resource requirements, and major program decisions.
• Experience mentoring Technical Program Managers or serving as a technical/program leadership resource across an organization.
• Familiarity with Agile, hybrid Agile/Waterfall, or other scaled execution methodologies within hardware and semiconductor development environments

Job Type:
Regular

Shift:
Shift 1 (United States of America)

Primary Location:
San Jose, California, United States

Additional Locations: