Advanced Micro Devices, Inc

Lead Embedded CPU PPA Architect

Advanced Micro Devices, Inc$162K — $195K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • Strong understanding of CPU and SoC architecture and PPA optimization.
  • Experience with power integrity and power delivery network design.
  • Knowledge of silicon reliability and thermal management methodologies.
  • Proven ability to lead cross-functional technical initiatives.

Responsibilities

  • Lead architecture for CPU Core and Cache complexes regarding power, performance, area, thermal, and reliability.
  • Drive alignment across various teams to establish targets for power delivery, thermal management, and performance.
  • Translate product workloads and system constraints into actionable objectives for power and performance.
  • Collaborate with modeling teams to define targets and assumptions, influencing architectural decisions.
  • Manage performance and power readiness for program milestones, overseeing technical reviews and risk management.

Benefits

  • Hybrid work environment in Santa Clara, CA.
  • Comprehensive AMD benefits package.
Full Job Description
THE ROLE:

We are seeking a Lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meets the product performance requirements while operating within reliability and system platform constraints. This is a technical leadership role ensuring interlock between CPU IP definition from the Cores design team and the Embedded BU's unique per-product usage model and operating conditions, and the package & platform impact to the power delivery network and thermal management.

THE PERSON:

You will be a proven technical leader with the ability to drive cross-functional alignment and execution across architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, ensuring timely closure and multi-dimensional alignment of reliability, power delivery, thermal management and performance constraints. You will also be highly organized and execution-driven, with demonstrated success owning end-to-end technical workstreams and driving closure of open issues, risks, and dependencies across program milestones.

KEY RESPONSIBILITIES
  • Lead power, performance, area (PPA), thermal, and reliability architecture for CPU Core and Cache complexes, ensuring alignment between product usage models, operating conditions, platform constraints, and CPU IP capabilities.
  • Drive cross-functional alignment across CPU architecture, physical design, FW/BIOS, SIPI, package, and platform teams to establish power delivery, thermal management, and performance targets that enable efficient and reliable product operation.
  • Translate product workloads, reliability requirements, and system constraints into actionable power, performance, and thermal objectives, influencing SoC, package, and platform architectural decisions while driving alignment between Embedded product roadmaps and available CPU IP solutions.
  • Partner closely with power and performance modeling, power delivery, thermal, and reliability teams to define assumptions, targets, and operating conditions, using modeling insights to drive architectural tradeoffs, bounding box readiness, and program execution.
  • Own performance and power readiness for major program milestones, driving technical reviews, risk management, issue resolution, and executive-level decision making across the product development lifecycle.

PREFERRED EXPERIENCE
  • Strong understanding of CPU and SoC architecture, including power delivery, PPA optimization, performance states, low-power modes, thermal management, and platform-level constraints.
  • Experience with power integrity (PI), power delivery network (PDN) design, and system-level power management concepts, including IR drop, voltage droop, impedance optimization, decoupling strategies, and noise budgeting.
  • Knowledge of silicon reliability, thermal management methodologies, and the interactions between silicon, package, and platform design required to achieve robust product operation.
  • Proven ability to lead complex cross-functional technical initiatives across architecture, design, firmware, validation, package, and platform engineering organizations.
  • Experience collaborating with power and performance modeling teams to drive target setting, architectural tradeoffs, and product optimization, along with ownership of technical workstreams through key product development milestones.

ACADEMIC CREDENTIALS

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

LOCATION:

Santa Clara, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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