BS in Electrical Engineering (5+ years experience) OR MS (3+ years experience)
Proficiency with Cadence tools: Innovus, Tempus, QRC, Voltus, Pegasus
Experience with cutting-edge technologies (5nm, 3nm, 2nm nodes)
Familiarity with Linux servers and scripting (Shell/Perl/TCL/Python)
In-depth knowledge of industry standard interfaces (PCI Express, DDR, LPDDR, SRAM, UCIe)
Responsibilities
Implement and verify hardware for Palladium and Protium SOCs
Perform RTL synthesis and floorplanning
Build and optimize clock trees
Achieve timing closure and conduct IR drop verification
Document designs for successful tape-out
Collaborate with front-end RTL design and back-end verification teams
Full Job Description
Job Responsibility
Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.
Work on RTL synthesis and floorplanning
Build clock trees and perform optimizations
Close timing, IR drop and physical verification
Review and Document designs for taping out
Interface with Front End RTL design teams and Back End Verification teams
Position Requirements/Qualifications:
BS degree in Electrical Engineering with a minimum of 5 years of experience OR MS with a minimum of 3 years of experience
Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
Experience with advanced technologies like 5nm, 3ns and 2nm nodes
Experience using Linux servers, Script development using Shell/Perl/TCL/Python
Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.
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About Cadence Design Systems
Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
