Bachelor's, Master's, or Ph.D. in Electrical Engineering, Physics, Materials Science, Optical Engineering, or related field.
5+ years of semiconductor layout design experience.
3+ years of experience with III-V optoelectronic devices preferred.
Proven experience in developing production mask sets and managing layout releases.
Strong understanding of semiconductor fabrication processes and their impact on layout.
Responsibilities
Lead development of physical layouts for III-V semiconductor laser products.
Own layout architecture and mask design from concept to production.
Develop and improve design rule methodologies and verification flows.
Design process monitor structures and test patterns for process control.
Automate design rule checks and data analysis using programming languages.
Collaborate with cross-functional teams to meet design and manufacturing requirements.
Mentor layout engineering techs on methodologies and compliance.
Benefits
Opportunity to work with cutting-edge optoelectronic technologies.
Collaborative environment with cross-functional teams.
Mentorship opportunities for professional growth.
Involvement in layout automation initiatives to enhance productivity.
Exposure to a variety of semiconductor fabrication processes.
Full Job Description
Job Description
Primary Duties & Responsibilities
Lead physical layout development for III-V semiconductor laser products including VCSELs, DFB lasers, photonic devices, and related optoelectronic technologies.
Own layout architecture, mask design, and mask data preparation from concept through production release.
Develop, maintain, and improve design rule methodologies, verification flows, and layout standards to ensure manufacturable and robust designs.
Design and implement process monitor structures, test patterns, and characterization vehicles to support process development, process control, yield improvement, and reliability monitoring.
Develop automated Design Rule Check (DRC), Layout Versus Schematic (LVS), verification, and data analysis solutions using scripting and programming languages such as Python, Tcl, Perl, or equivalent.
Champion layout automation initiatives to improve design productivity, consistency, quality, and cycle time.
Collaborate closely with process integration, device engineering, epitaxy, manufacturing, and product engineering teams to ensure layouts meet design, process, reliability, and manufacturing requirements.
Drive layout reviews and cross-functional design reviews throughout product development and qualification phases.
Support root cause investigations and failure analysis activities by evaluating potential layout-related issues and implementing corrective actions.
Establish and maintain layout design guidelines, libraries, reusable cells, and best practices.
Coordinate mask revisions and change management activities while ensuring configuration control and documentation accuracy.
Lead multifunctional teams in resolving layout, manufacturability, and process integration challenges.
Mentor layout engineering techs and provide technical guidance on layout methodologies, DRC compliance, automation, and semiconductor process interactions.
Education & Experience
Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Physics, Materials Science, Optical Engineering, or a related technical field.
Minimum 5 years of semiconductor layout design experience required.
Minimum 3 years of direct experience with III-V optoelectronic devices such as VCSELs, DFB lasers, edge-emitting lasers, photonic integrated circuits (PICs), or similar technologies preferred.
Demonstrated experience developing production mask sets and managing layout releases for semiconductor products.
Experience designing process control monitor (PCM) structures, test keys, and process characterization patterns.
Strong understanding of semiconductor fabrication processes and how process interactions impact physical layout and device performance.
Skills
Expert-level experience with semiconductor layout tools, preferably Silvaco layout solutions. Experience with equivalent EDA platforms such as Cadence, KLayout, Synopsys, Mentor Graphics/Siemens EDA, or similar tools will also be considered.
Strong understanding of physical layout design principles, mask design, DRC, LVS, and semiconductor manufacturing constraints. Proficiency in programming and automation using Python, Tcl, Perl, C++, or similar languages.
Hands-on experience with VCSEL, DFB laser, photonic integrated circuit (PIC), or related optoelectronic device layouts.
Strong knowledge of lithography, etch, metallization, dielectric deposition, implantation, and other semiconductor fabrication processes.
Familiarity with semiconductor manufacturing operations, process control methodologies, and change management systems.
Strong analytical and problem-solving skills with the ability to evaluate complex layout-process interactions.
Excellent communication and leadership skills with demonstrated ability to influence and drive actions across multifunctional engineering teams.
Self-motivated and capable of leading projects in a fast-paced product development environment.
Experience with statistical analysis tools such as JMP, Minitab, or equivalent is a plus.
Working Conditions
Normal office environment
Physical Requirements
Work in a class 100/1000 clean room for extended periods
Wear full cleanroom attire (smock, mask, etc.)
Work with and/or around chemicals (such as solids and acids)
Stand for up to 4 hours at a time
Lift up to 16-30 Pounds
Push/Pull up to 16-30 pounds
Sit for up to 4 hours at a time
Safety Requirements
All employees are required to follow the site EHS procedures and Coherent Corp. Corporate EHS standards.
Quality and Environmental Responsibilities
Depending on location, this position may be responsible for the execution and maintenance of the ISO 9000, 9001, 14001 and/or other applicable standards that may apply to the relevant roles and responsibilities within the Quality Management System and Environmental Management System.
