Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Qualcomm Central Hardware Systems (CHS) is seeking a Senior Lead High-speed Electrical/Optical Post-Silicon Engineer to drive hands-on measurements, validation, and debug of next-generation 224G/448G electrical and optical interconnects. The role spans channel characterization, passive measurements, SerDes validation, PDN debug, and SW/HLOS-driven system validation.
Key Responsibilities- High-speed measurements and channel correlation: Plan and drive 224G/448G electrical/optical measurements and channel characterization across package, PCB, connector, cable, optical module, and system channels. Analyze S-parameters, loss, impedance, skew, crosstalk, jitter/noise, reflections, eye margin, and link robustness; correlate bench data to simulations and package/board models.
- Post-silicon bring-up and system validation: Lead bring-up, characterization, margining, shmoo, stress, compliance-readiness, and SW/HLOS-level validation across reference boards, optical modules, retimers, active/passive cables, and customer-like platforms. Validate tuning, link training, equalization, calibration, FEC/error counters, and workload traffic patterns.
- PDN and cross-functional system debug: Drive PDN measurement and failure isolation across self-noise, coupling, rail droop/ripple, sequencing, package/board power delivery, SI/PI, optics, firmware, drivers, clocking, thermal, software workloads, and platform integration. Translate ambiguous lab/field signatures into RCA hypotheses and debug plans.
- Validation content and automation: Develop automation, data reduction scripts, dashboards, regression flows, and stress content to reproduce, isolate, and prevent electrical/optical/PDN failures.
- Cross-functional leadership: Work with SerDes PHY, SIPI/PDN, package, PCB, optics, firmware, software, validation, systems architecture, platform, customer engineering, suppliers, and ecosystem partners to drive closure.
Required Qualifications- 8+ years of relevant experience in post-silicon, SI/PI, SerDes/DDR, optical, package/PCB, or system validation.
- Strong fundamentals in high-speed digital design, SerDes/DDR PHYs, SI/PI, transmission lines, jitter/noise, equalization, channel modeling, and measurement correlation.
- Hands-on experience with VNAs, oscilloscopes, BERTs, TDR/TDT, rail probing, spectrum analyzers, optical BER/power test equipment, and precision probing/fixturing.
- Experience validating and debugging high-speed links such as DDR, PCIe/CXL, Ethernet, UCIe/chip-to-chip, optical module interfaces, retimers, or similar SerDes-based interfaces.
- Strong PDN/system debug experience, including rail noise/ripple, droop/coupling, sequencing, package/board PDN behavior, and workload-driven power stress.
Preferred Qualifications- Experience with 112G/224G/448G-class SerDes, PAM4/PAM6/PAM8 signaling, DSP-based SerDes, optical module host interfaces, and advanced equalization/calibration.
- Experience with IEEE Ethernet, DDR, PCIe/CXL, UCIe, or similar high-speed electrical/optical standards and debug methodologies.
- Experience with optical/electrical co-validation, module bring-up, optical link debug, electrical-to-optical correlation, retimer/re-driver tuning, and link budget closure.
- Experience with package/PCB test vehicles, socketed and solder-down platforms, passive/active measurements, and DOE-based characterization.
- Experience driving complex customer, supplier, or platform escalations where root cause spans silicon, package, board, firmware, software, thermal, and system conditions.
- Familiarity with Linux, UEFI, HLOS validation, embedded instrumentation, telemetry collection, and stress workloads.
Experience / Impact- Accelerate post-silicon bring-up and issue closure for next-generation high-speed electrical and optical interconnects.
- Improve confidence in 224G/448G channel, package, PCB, optical, PDN, and system readiness.
- Reduce late-stage surprises by connecting measurements, validation content, and design feedback across silicon, package, board, software, and platform teams.
- Build reusable validation and debug methods that scale across products, suppliers, test vehicles, and customer platforms.
- Produce concise technical and executive reports covering measurements, findings, risk, RCA status, and recommended actions.
Minimum Qualifications:• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Software Applications Engineering, Software Development experience, or related work experience.
OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Software Applications Engineering, Software Development experience, or related work experience.
OR
PhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Applications Engineering, Software Development experience, or related work experience.
• 4+ years of experience with Programming Language such as C, C++, Java, Python, etc.
• 4+ years of experience with debugging techniques.
Pay range and Other Compensation & Benefits: $192,000.00 - $288,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
